AT24C256B ATMEL Corporation, AT24C256B Datasheet
AT24C256B
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AT24C256B Summary of contents
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Features • Low-voltage and Standard-voltage Operation, V • Internally Organized 16,384 x 8 and 32,768 x 8 • 2-wire Serial Interface • Schmitt Trigger, Filtered Inputs for Noise Suppression • Bi-directional Data Transfer Protocol • 1 MHz (5V) and 400 ...
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Absolute Maximum Ratings* Operating Temperature Storage Temperature Voltage on Any Pin with Respect to Ground Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA Pin Description Memory Organization AT24C128SC/AT24C256SC 2 *NOTICE +125 ...
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Pin Capacitance (1) Table 2. Pin Capacitance Applicable over recommended operating range from T Symbol Test Condition C Input/Output Capacitance (SDA) I/O C Input Capacitance (SCL) IN Note: This parameter is characterized and is not 100% tested. DC Characteristics (1) ...
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AC Characteristics (1) Table 4. AC Characteristics Symbol Parameter f Clock Frequency, SCL SCL t Clock Pulse Width Low LOW t Clock Pulse Width High HIGH t Clock Low to Data Out Valid AA Time the bus must be free ...
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Device Operation 1661B–SEEPR–04/04 CLOCK AND DATA TRANSITIONS: The SDA pin is normally pulled high with an exter- nal device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes ...
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Timing Diagrams Bus Timing Write Cycle Timing Data Validity AT24C128SC/AT24C256SC 6 Figure 3. Bus Timing Note: SCL: Serial Clock; SDA: Serial Data I/O Figure 4. Write Cycle Timing Note: 1. The write cycle time t is the time from a ...
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Start and Stop Definition Output Acknowledge 1661B–SEEPR–04/04 Figure 6. Start and Stop Definition SDA SCL START Figure 7. Output Acknowledge SCL DATA IN DATA OUT START AT24C128SC/AT24C256SC ACKNOWLEDGE STOP 7 ...
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Device Addressing Write Operations AT24C128SC/AT24C256SC 8 The 128K/256K EEPROM requires an 8-bit device address word following a start condi- tion to enable the chip for a read or write operation (refer to Figure 8). The device address word consists of ...
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Figure 10. Page Write Note DON’T CARE bit 2. † = DON’T CARE bit for the 128K Read Operations 1661B–SEEPR–04/04 ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling ...
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Figure 12. Random Read Notes DON’T CARE bit 2. † = DON’T CARE bit for the 128K Figure 13. Sequential Read AT24C128SC/AT24C256SC 10 address and serially clocks out the data word. The microcontroller does not respond with ...
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AT24C128SC Ordering Information Ordering Code AT24C128SC-09AT M2 – A Module AT24C128SC-09BT M2 – B Module AT24C128SC-10WI 7 mil Wafer AT24C256SC Ordering Information Ordering Code AT24C256SC-09AT M2 – A Module AT24C256SC-09BT M2 – B Module AT24C256SC-10WI 7 mil Wafer (1) Description ...
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Smart Card Modules Ordering Code: 09AT-00 Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square: 8.6 x 8.6 [mm] Thickness: 0.58 [mm] max Pitch: 14.25 [mm] *Note: The module dimensions listed refer to the dimensions of the exposed ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibil ity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wit h out notice, and does not make any commitment to update the information contained herein ...