ATMEGA16L ATMEL Corporation, ATMEGA16L Datasheet
ATMEGA16L
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ATMEGA16L Summary of contents
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... ATmega16L – 4.5 - 5.5V for ATmega16 • Speed Grades – MHz for ATmega16L – MHz for ATmega16 • Power Consumption @ 1 MHz, 3V, and 25 C for ATmega16L – Active: 1.1 mA – Idle Mode: 0.35 mA – Power-down Mode: < 1 µA ® 8-bit Microcontroller 8-bit ...
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Pin Configurations Figure 1. Pinouts ATmega16 Disclaimer Typical values contained in this data sheet are based on simulations and characteriza- tion of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the ...
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Overview Block Diagram 2466F–AVR–02/03 The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system ...
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in ...
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Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF About Code Examples 2466F–AVR–02/03 Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have ...
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AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and ...
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ALU Arithmetic Logic – Unit Status Register 2466F–AVR–02/03 an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly ...
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Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individ- ual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable ...
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General Purpose Register File 2466F–AVR–02/03 The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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The X-register, Y-register and The registers R26..R31 have some added functions to their general purpose usage. Z-register These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are ...
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Instruction Execution Timing Reset and Interrupt Handling 2466F–AVR–02/03 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. Figure ...
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External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 43 for more ...
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Interrupt Response Time 2466F–AVR–02/03 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set global interrupt enable sleep ; enter ...
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AVR ATmega16 This section describes the different memories in the ATmega16. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In Memories addition, the ATmega16 features an EEPROM Memory for data storage. All ...
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SRAM Data Memory 2466F–AVR–02/03 Figure 9 shows how the ATmega16 SRAM Memory is organized. The lower 1120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File ...
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Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 10. Figure 10. On-chip Data SRAM Access Cycles EEPROM Data Memory The ATmega16 contains ...
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The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR 2466F–AVR–02/03 Bit – – – EEAR7 EEAR6 EEAR5 Read/Write R/W R/W ...
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When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. • Bit 1 – EEWE: EEPROM Write Enable The ...
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The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by dis- abling interrupts globally) so that no interrupts will occur during execution of ...
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. EEPROM Write During Power- When entering Power-down Sleep mode ...
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I/O Memory 2466F–AVR–02/ llo ...
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System Clock and Clock Options Clock Systems and their Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, ...
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Asynchronous Timer Clock – clk ASY ADC Clock – clk ADC Clock Sources Default Clock Source Crystal Oscillator 2466F–AVR–02/03 The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated ...
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This mode has a limited frequency range and it can not be used to drive other clock buffers. For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always ...
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The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and CKSEL0 SUT1..0 Power-save ( 258 ...
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Low-frequency Crystal To use a 32.768 kHz watch crystal as the clock source for the device, the Low-fre- quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The Oscillator crystal should be connected as shown in ...
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Calibrated Internal RC Oscillator 2466F–AVR–02/03 Table 7. External RC Oscillator Operating Modes CKSEL3..0 0110 0111 1000 When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8. Table 8. Start-up Times for the ...
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When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 10. XTAL1 and XTAL2 should be left unconnected (NC). Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection Note: Oscillator ...
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External Clock Timer/Counter Oscillator 2466F–AVR–02/03 To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be pro- grammed to “0000”. ...
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Power Management Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the and Sleep Modes power consumption to the application’s requirements. To ...
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Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode 2466F–AVR–02/03 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two- wire ...
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Asynchronous Timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk chronous modules, including Timer/Counter2 if clocked asynchronously. Standby Mode When the SM2..0 bits are 110 and ...
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Minimizing Power Consumption Analog to Digital Converter Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins 2466F–AVR–02/03 There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep ...
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On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse, and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly ...
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System Control and Reset Resetting the AVR Reset Sources 2466F–AVR–02/03 During Reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be ...
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... V production test. This guarantees that a Brown-out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 1 for ATmega16L and BODLEVEL = 0 for ATmega16. BODLEVEL = 1 is not applicable for ATmega16. DATA BUS ...
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Power-on Reset 2466F–AVR–02/03 A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 15. The POR is activated whenever V detection level. The POR circuit can be used to trigger ...
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External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not running. Shorter pulses are ...
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Watchdog Reset MCU Control and Status Register – MCUCSR 2466F–AVR–02/03 When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting ...
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Internal Voltage ATmega16 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. The Reference 2.56V reference to the ADC is generated ...
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Watchdog Timer Control Register – WDTCR 2466F–AVR–02/03 Bit – – – Read/Write Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will ...
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The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. ...
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Interrupts Interrupt Vectors in ATmega16 2466F–AVR–02/03 This section describes the specifics of the interrupt handling as performed in ATmega16. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11. Table 18. Reset ...
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Table 19. Reset and Interrupt Vectors Placement Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega16 is: ATmega16(L) 44 BOOTRST IVSEL Reset address 1 0 $0000 1 1 $0000 0 0 Boot ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset ...
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Moving Interrupts Between The General Interrupt Control Register controls the placement of the Interrupt Vector Application and Boot Space table. General Interrupt Control Register – GICR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared ...
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Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL ...
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I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with ...
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Ports as General Digital I/O Configuring the Pin 2466F–AVR–02/03 The ports are bi-directional I/O ports with optional internal pull-ups. Figure 23 shows a functional description of one I/O-port pin, here generically called Pxn. (1) Figure 23. General Digital I/O Pxn ...
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If this is not the case, the PUD bit in the SFIOR Register can be set to ...
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As indicated by the two arrows t single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned ...
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned to port pins 6 and 7. The ...
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Unconnected pins Alternate Port Functions 2466F–AVR–02/03 If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, ...
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Table 21 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table 21. ...
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Special Function I/O Register – SFIOR Alternate Functions of Port A 2466F–AVR–02/03 Bit ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W Initial Value • Bit 2 – PUD: Pull-up disable When this bit is written ...
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Table 24. Overriding Signals for Alternate Functions in PA3..PA0 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 25. Table 25. Port B Pins Alternate Functions The alternate pin configuration is as follows: ...
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DDB6. When the pin is forced by the SPI input, the pull-up can still be con- trolled by the PORTB6 bit. • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input ...
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Table 26. Overriding Signals for Alternate Functions in PB7..PB4 Table 27. Overriding Signals for Alternate Functions in PB3..PB0 ATmega16(L) 58 Signal Name PB7/SCK PB6/MISO PUOE SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB6 • PUD DDOE SPE ...
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Alternate Functions of Port C 2466F–AVR–02/03 The Port C pins with alternate functions are shown in Table 28. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be acti- vated even if a ...
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SDA – Port C, Bit 1 SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data I/O ...
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Alternate Functions of Port D 2466F–AVR–02/03 Table 30. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PC3/TMS PC2/TCK PUOE JTAGEN JTAGEN PUOV 1 1 DDOE JTAGEN JTAGEN DDOV 0 0 PVOE 0 0 PVOV 0 0 DIEOE JTAGEN JTAGEN ...
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OC1A – Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) ...
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Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB 2466F–AVR–02/03 Table ...
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Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD ...
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External Interrupts MCU Control Register – MCUCR 2466F–AVR–02/03 The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides ...
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Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level ...
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General Interrupt Flag Register – GIFR 2466F–AVR–02/03 ISC10) in the MCU General Control Register (MCUCR) define whether the External Interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause ...
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Timer/Counter0 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: with PWM • • • • • • • Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27. For ...
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Definitions Timer/Counter Clock Sources Counter Unit 2466F–AVR–02/03 The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the wave- form generator to generate a PWM ...
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Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02 the timer ...
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Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit 2466F–AVR–02/03 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) ...
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Compare Match Output The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera- tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next Unit compare match. Also, the COM01:0 bits control the OC0 ...
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Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2466F–AVR–02/03 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and ...
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CTC mode does not have the double buffering feature. If the new value written to OCR0 is lower than the current ...
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Figure 32. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM01 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual- slope operation. The counter counts repeatedly from BOTTOM ...
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OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f OCn PCPW M The N variable represents the prescale factor (1, 8, 64, ...
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Timer/Counter Timing The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information Diagrams on when Interrupt Flags are set. Figure 34 contains timing data for ...
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Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. ...
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Timer/Counter Register Description Timer/Counter Control Register – TCCR0 • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit ...
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When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 39 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). ...
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Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 42. Clock Select Bit Description If external pin modes are used for the Timer/Counter0, transitions on the ...
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Timer/Counter Interrupt Flag Register – TIFR 2466F–AVR–02/03 executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When ...
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Timer/Counter0 and Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counter1 both Timer/Counter1 and Timer/Counter0. Prescalers Internal Clock Source The Timer/Counter can be clocked directly by the ...
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Special Function IO Register – SFIOR 2466F–AVR–02/03 than half the system clock frequency (f the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to ...
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The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: Timer/Counter1 • • • • • • • • • • • Overview Most register and bit ...
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Registers 2466F–AVR–02/03 Figure 40. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 25 on page 56, and Table 31 on page 61 for ...
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See “Output Compare Units” on page 95. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an output com- pare interrupt request. The Input Capture Register can capture the Timer/Counter ...
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Accessing 16-bit Registers 2466F–AVR–02/03 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: The assembly code example returns the TCNT1 ...
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Reusing the Temporary High Byte Register Timer/Counter Clock Sources 2466F–AVR–02/03 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 41 shows a block diagram of the counter and its surroundings. Figure 41. Counter Unit Block Diagram Signal description (internal signals): The 16-bit ...
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Input Capture Unit 2466F–AVR–02/03 The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 ...
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For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 89. Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively ...
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Output Compare Units 2466F–AVR–02/03 The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock ...
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Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte temporary register (TEMP). However ...
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Compare Match Output Unit Compare Output Mode and Waveform Generation 2466F–AVR–02/03 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. ...
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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits ...
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Fast PWM Mode 2466F–AVR–02/03 Figure 45. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period 1 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to ...
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 ...
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Phase Correct PWM Mode 2466F–AVR–02/03 The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around start- ing at ...
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OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the ...
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Phase and Frequency Correct PWM Mode 2466F–AVR–02/03 ing slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the ...
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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and ...
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Timer/Counter Timing Diagrams 2466F–AVR–02/03 inverted PWM and an inverted PWM output can be generated by setting the COM1x1 (See Table on page 109). The actual OC1x value will only be visible on the port pin if the data ...
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Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing ...
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Figure 52. Timer/Counter Timing Diagram, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx ...
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Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare ...
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Table 45. Compare Output Mode, Fast PWM COM1A1/COM1B1 COM1A0/COM1B0 Note special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, ...
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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 1:0 – WGM11:0: Waveform ...
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Timer/Counter1 Control Register B – TCCR1B 2466F–AVR–02/03 Bit ICNC1 ICES1 – Read/Write R/W R/W R Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input ...
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Table 48. Clock Select Bit Description (Continued) If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of ...
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Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask (1) Register – TIMSK 2466F–AVR–02/03 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each ...
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Timer/Counter Interrupt Flag Register – TIFR Note: • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 ...
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Timer/Counter2 with PWM and Asynchronous Operation Overview Registers 2466F–AVR–02/03 Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct ...
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The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the wave- form generator to generate a PWM or variable frequency output on the Output ...
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Output Compare Unit 2466F–AVR–02/03 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock ...
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The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of ...
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Compare Match Output Unit Compare Output Mode and Waveform Generation 2466F–AVR–02/03 The Compare Output mode (COM21:0) bits have two functions. The Waveform Genera- tor uses the COM21:0 bits for defining the Output Compare (OC2) state at the next compare match. ...
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Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits ...
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Fast PWM Mode 2466F–AVR–02/03 care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the com- pare match. The ...
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The Timer/Counter Overflow Flag ( the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the ...
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Figure 59. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 1 The Timer/Counter Overflow Flag ( TOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase ...
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Timer/Counter Timing The following figures show the Timer/Counter in Synchronous mode, and the timer clock Diagrams (clk be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 60 contains timing data ...
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Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRn - 1 OCRn OCFn Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. ...
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Timer/Counter Register Description Timer/Counter Control Register – TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit ...
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When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 51 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). ...
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Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 54. Table 54. Clock Select Bit Description Timer/Counter Register – TCNT2 The Timer/Counter Register gives direct ...
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Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Asynchronous Operation of Timer/Counter2 2466F–AVR–02/03 Bit – – – Read/Write Initial Value • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 ...
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ATmega16(L) 130 6. Enable interrupts, if needed. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. ...
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Timer/Counter Interrupt Mask Register – TIMSK 2466F–AVR–02/03 from Power-save mode, and the I/O clock (clk read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save ...
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Timer/Counter Interrupt Flag Register – TIFR • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is ...
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Special Function IO Register – SFIOR 2466F–AVR–02/03 For Timer/Counter2, the possible prescaled selections are: clk clk /128, clk /256, and clk /1024. Additionally, clk T2S T2S T2S selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the ...
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Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16 and peripheral devices or between several AVR devices. The Interface – SPI ATmega16 SPI includes the following features: • • • • • • • ...
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When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register ...
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The following code examples show how to initialize the SPI as a Master and how to per- form a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO ...
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The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable ...
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SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the ...
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Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is ...
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SPI Status Register – SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If ...
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Data Modes 2466F–AVR–02/03 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. Data ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • • • • • • • • • • • • Overview A simplified block diagram of ...
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AVR USART vs. AVR UART – Compatibility Clock Generation 2466F–AVR–02/03 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all ...
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Figure 70. Clock Generation Logic, Block Diagram Signal description: Internal Clock Generation – Internal clock generation is used for the asynchronous and the synchronous Master The Baud Rate Generator modes of operation. The description in this section refers to Figure ...
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Double Speed Operation (U2X) External Clock 2466F–AVR–02/03 Table 60. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal Mode (U2X = 0) Asynchronous Double Speed Mode (U2X = 1) Synchronous Master Mode Note: 1. The baud rate is ...
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Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the ...
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Parity Bit Calculation USART Initialization 2466F–AVR–02/03 IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0, and USBS bits in UCSRB ...
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Note: More advanced initialization routines can be made that include frame format as parame- ters, disable interrupts and so on. However, many applications use a fixed setting of the Baud and Control Registers, and for these types of applications the ...
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Data Transmission – The USART Transmitter Sending Frames with Data Bit 2466F–AVR–02/03 The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation ...
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Sending Frames with 9 Data If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in Bit UCSRB before the Low byte of the character is written to UDR. The following code ...
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Parity Generator Disabling the Transmitter 2466F–AVR–02/03 empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted ...
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Data Reception – The The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the receiver is enabled, the normal pin operation of the USART Receiver RxD pin is overridden by ...
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Receiving Frames with 9 Databits 2466F–AVR–02/ bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR ...
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The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as ...
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Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery 2466F–AVR–02/03 The PE bit is set if the next character that can be read from the receive buffer had a par- ity error when received and the ...
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Figure 73. Start Bit Sampling When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam- ple as shown in ...
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Asynchronous Operational Range 2466F–AVR–02/03 Figure 75. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop ...
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Table 61 and Table 62 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode ...
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Multi-processor Communication Mode Using MPCM 2466F–AVR–02/03 Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not ...
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Accessing UBRRH/ The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. UCSRC Registers Write Access When doing a write access of this I/O location, the ...
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Read Access USART Register Description USART I/O Data Register – UDR 2466F–AVR–02/03 Doing a read access to the UBRRH or the UCSRC Register is a more complex opera- tion. However, in most applications rarely necessary to read any ...
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The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When data is written to ...
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USART Control and Status Register B – UCSRB 2466F–AVR–02/03 • Bit 2 – PE: Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled ...
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When disabled, the transmitter will no longer over- ride the TxD port. • Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of ...
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Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the transmit- ter will automatically generate and send the parity of the transmitted data bits within each frame. The ...
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Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and ...
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Examples of Baud Rate Setting Table 68. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% ...
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Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
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Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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Two-wire Serial Interface Features Two-wire Serial Interface Bus Definition TWI Terminology 2466F–AVR–02/03 • Simple Yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device Can Operate as Transmitter or Receiver ...
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Electrical Interconnection As depicted in Figure 76, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to ...
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Address Packet Format 2466F–AVR–02/03 Figure 78. START, REPEATED START, and STOP Conditions SDA SCL START All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. ...
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Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while ...
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Multi-master Bus Systems, Arbitration and Synchronization 2466F–AVR–02/03 The TWI protocol allows bus systems with several Masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more Masters initiate a transmission ...
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Figure 83. Arbitration between Two Masters Note that arbitration is not allowed between: • • • the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers ...
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Overview of the TWI Module SCL and SDA Pins Bit Rate Generator Unit 2466F–AVR–02/03 The TWI module is comprised of several submodules, as shown in Figure 84. All regis- ters drawn in a thick line are accessible through the AVR ...
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Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Con- troller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In ...
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TWI Register Description TWI Bit Rate Register – TWBR TWI Control Register – TWCR 2466F–AVR–02/03 Bit TWBR7 TWBR6 TWBR5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 – TWI Bit Rate Register TWBR ...
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STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • Bit 4 – TWSTO: TWI STOP Condition ...
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TWI Data Register – TWDR TWI (Slave) Address Register – TWAR 2466F–AVR–02/03 • Bits 1..0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 73. TWI Bit Rate Prescaler TWPS1 ...
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Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts ...
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The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates other- wise, the application software might take some special action, like calling an error routine. ...
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In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made, for example by using include-files. Assembly code example ldi r16, (1<<TWINT)|(1<<TWSTA)| 1 (1<<TWEN) out TWCR, ...
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Transmission Modes Master Transmitter Mode 2466F–AVR–02/03 The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in ...
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Figure 86. Data Transfer in Master Transmitter Mode A START condition is sent by writing the following value to TWCR: TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START ...
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Table 74. Status Codes for Master Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware $08 A START condition has been transmitted $10 A repeated START condition has ...
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Figure 87. Formats and States in the Master Transmitter Mode Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Trans- mitter (see Figure 88). In order to enter a Master mode, ...
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Figure 88. Data Transfer in Master Receiver Mode Device 1 Device 2 MASTER SLAVE RECEIVER TRANSMITTER SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA Value TWEN ...
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Table 75. Status Codes for Master Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware $08 A START condition has been transmitted $10 A repeated START condition has ...
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Slave Receiver Mode 2466F–AVR–02/03 Figure 89. Formats and States in the Master Receiver Mode MR Successfull S SLA R A reception from a slave receiver $08 $40 Next transfer started with a repeated start condition Not acknowledge A received after ...
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The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the ...
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Table 76. Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware $60 Own SLA+W has been received; ACK has been returned $68 Arbitration lost in ...
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Figure 91. Formats and States in the Slave Receiver Mode Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 92). All the status codes mentioned in this section ...
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The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore ...
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Table 77. Status Codes for Slave Transmitter Mode Status Code (TWSR) Status of the Two-wire Serial Bus Prescaler Bits and Two-wire Serial Interface are 0 Hardware $A8 Own SLA+R has been received; ACK has been returned $B0 Arbitration lost in ...
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Miscellaneous States Table 78. Miscellaneous States Status Code (TWSR) Status of the Two-wire Serial Prescaler Bits Bus and Two-wire Serial Inter- are 0 face Hardware $F8 No relevant state information available; TWINT = “0” $00 Bus error due to an ...
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Combining Several TWI In some cases, several TWI modes must be combined in order to complete the desired Modes action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer ...
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Several different scenarios may arise during arbitration, as described below: • Two or more Masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the Masters will know about the bus ...
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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...