K9K4G08U0M-PCB0 Samsung, K9K4G08U0M-PCB0 Datasheet
K9K4G08U0M-PCB0
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K9K4G08U0M-PCB0 Summary of contents
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... The 5th Byte ID after 90h ID read command is deleted. 0.3 1. The K9W8G16U1M-YCB0,YIB0,PCB0,PIB0 is deleted in line up. 2. Note is added. (VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations less.) 3. Pb-free Package is added. K9K4G08Q0M-PCB0,PIB0 K9K4G08U0M-PCB0,PIB0 K9K4G16U0M-PCB0,PIB0 K9K4G16Q0M-PCB0,PIB0 K9W8G08U1M-PCB0,PIB0 0.4 1. Added Addressing method for program operation. 0.5 1. The tADL(Address to Data Loading Time) is added. ...
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... Unique ID for Copyright Protection • Package : - K9K4G08U0M-YCB0/YIB0 48 - Pin TSOP I ( 0.5 mm pitch) - K9W8G08U1M-YCB0/YIB0 : Two K9K4G08U0M stacked Pin TSOP I ( 0.5 mm pitch) - K9K4G08U0M-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I ( 0.5 mm pitch) - K9W8G08U1M-PCB0/PIB0 : Two K9K4G08U0M stacked Pin TSOP I ( 0.5 mm pitch) 2 FLASH MEMORY ...
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... K9W8G08U1M K9K4G08U0M PIN CONFIGURATION (TSOP1) K9K4G08U0M-YCB0,PCB0/YIB0,PIB0 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220AF #1 #24 0~8° 0.45~0.75 0.018~0.030 ...
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... K9W8G08U1M K9K4G08U0M PIN CONFIGURATION (TSOP1) K9W8G08U1M-YCB0,PCB0/YIB0,PIB0 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 R/ CE1 9 CE2 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220AF #1 #24 0~8° 0.45~0.75 0.018~0.030 48 47 ...
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... CE1 control during read operation, refer to ’Page read’ section of Device operation . CHIP ENABLE CE2 The CE2 input enables the second K9K4G08U0M READ ENABLE RE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one ...
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... K9W8G08U1M K9K4G08U0M Figure 1-1. K9K4G08U0M Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE PRE Figure 2-1. K9K4G08U0M Array Organization 256K Pages (=4,096 Blocks) ...
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... It indicates that the bit by bit erase operation is prohibited on the K9K4G08U0M. The K9K4G08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low ...
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... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, K9K4G08U0M-XCB0 Parameter Symbol ...
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... Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed valid block, does not require Error Correction program/erase cycles. Each K9K4G08U0M chip in the K9W8G08U1M has Maximum 80 invalid blocks TEST CONDITION (K9K4G08U0M-XCB0 :TA=0 to 70° ...
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... NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low. 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. 3. For cache program operation, the whole AC Charcateristics must be same as that of K9K4G08U0M*. Symbol ...
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... RHW WE High to RE Low t WHR Device Resetting Time t RST (Read/Program/Erase) NOTE reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. For cache program operation, the whole AC Charcateristics must be same as that of K9K4G08U0M*. Min K9K4G08U0M* K9K4G08U0M - - ...
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... K9W8G08U1M K9K4G08U0M NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9W8G08U1M K9K4G08U0M NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done ...
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... K9W8G08U1M K9K4G08U0M NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...
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... K9W8G08U1M K9K4G08U0M NAND Flash Technical Notes Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig- nificant bit) pages of the block. Random page address programming is prohibited. (64) Page 63 : (32) ...
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... K9W8G08U1M K9K4G08U0M System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption ...
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... K9W8G08U1M K9K4G08U0M NOTE I/O Device I/Ox K9K4G08U0M I I/O 7 Command Latch Cycle CLE CE WE ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE t DS I/Ox Col. Add1 DATA Data In/Out Col. Add1 Col. Add2 ~2112byte A0~A7 A8~A11 t t CLS CLH ...
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... K9W8G08U1M K9K4G08U0M Input Data Latch Cycle CLE ALE t ALS I/Ox DIN 0 Serial Access Cycle after Read t CEA CE t REA RE I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested ...
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... K9W8G08U1M K9K4G08U0M Status Read Cycle CLE I/Ox t CLR t CLS t CLH CEA t WHR IR* 70h 19 FLASH MEMORY t CHZ RHZ* REA t OH Status Output ...
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... K9W8G08U1M K9K4G08U0M Read Operation CLE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R 30h Row Add1 Row Add2 Row Add3 Row Address ...
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... K9W8G08U1M K9K4G08U0M FLASH MEMORY 21 ...
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... K9W8G08U1M K9K4G08U0M Page Program Operation CLE ALE RE I/Ox 80h Co.l Add1 Col. Add2 Row Add1 SerialData Column Address Input Command R/B NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ADL Din ...
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... K9W8G08U1M K9K4G08U0M FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 23 ≈ ...
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... K9W8G08U1M K9K4G08U0M FLASH MEMORY ≈ ≈ ≈ ≈ 24 ...
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... K9W8G08U1M K9K4G08U0M ≈ ≈ FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 25 ...
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... K9W8G08U1M K9K4G08U0M BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 Row Address R/B Auto Block Erase Setup Command t t BERS WB D0h Busy Erase Command 26 FLASH MEMORY 70h I/O 0 I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase 0 Command ...
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... K9K4G08U0M Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle Device Device Code*(2nd Cycle) K9K4G08U0M DCh K9W8G08U1M Same as each K9K4G08U0M Defintition Table Access command = 90H Description Maker Code 1 Byte st Device Code 2 Byte nd 3 Byte Don’t care rd ...
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... K9W8G08U1M K9K4G08U0M 4th ID Data Description 1KB Page Size 2KB (w/o redundant area ) Reserved Reserved 64KB Blcok Size 128KB (w/o redundant area ) 256KB Reserved Redundant Area Size 8 ( byte/512byte Organization x16 50ns/30ns 25ns Serial AccessMinimum Reserved Reserved FLASH MEMORY I/O7 I/O6 I/O5 I/O4 I/ ...
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... K9W8G08U1M K9K4G08U0M Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25µ ...
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... K9W8G08U1M K9K4G08U0M Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 5Cycles Col Add1,2 & Row Add1,2,3 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array (1time/16byte) ...
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... K9W8G08U1M K9K4G08U0M Figure 9. Random Data Input In a Page R/B I/Ox Address & Data Input 80h Col Add1,2 & Row Add1,2,3 Data Cache Program Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell ...
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... K9W8G08U1M K9K4G08U0M NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple- tion of the previous cycle, which can be expressed as the following formula ...
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... K9W8G08U1M K9K4G08U0M BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address valid while address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... CLR t CEA t AR1 t WHR t Device REA ECh Code* Maker code Device code 3rd Cycle DCh C1h Same as each K9K4G08U0M RST After Power-up Low 00h command is latched 34 FLASH MEMORY C1h 4th Cyc.* 4th Cycle* 15h After Reset Waiting for next command ...
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... K9W8G08U1M K9K4G08U0M Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto- page read function. Auto-page read function is enabled only when PRE pin is tied to V without latency ...
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... K9W8G08U1M K9K4G08U0M READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9W8G08U1M K9K4G08U0M Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 18 ...
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... K9W8G08U1M K9K4G08U0M Extended Data Out Mode For the EDO mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that controller could fetch the data at the falling edge. However NAND flash dosen’t support the EDO mode exactly. ...