LC7185-8750 Sanyo Semiconductor Corporation, LC7185-8750 Datasheet
LC7185-8750
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LC7185-8750 Summary of contents
Page 1
... The specifications are suited for use in U.S.A.(FCC). Functions The LC7185-8750 incorporates PLL circuitry and a controller for CB applications on a single CMOS chip. The controller handles the PLL circuitry, frequency data ROM, channel preset/recall RAM, and LED display driver. It also supports channel scan, channel preset/recall, and emergency channel call ...
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... X’tal = 10.240 MHz TX = HOLD = INIT = V DD Other inputs = V SS Other outputs = open Note: Be careful that the dielectric strength of pins SA, SB, SC, SD, SE, SF, D1, D2, UL, BEEP are weak. LC7185-8750 SS Conditions Pins HOLD, TX Pin INIT Pins KI1, KI2, KI3, KI4 Pins HOLD, TX Pin INIT ...
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... Package Dimensions unit : mm 3061-DIP30S [LC7185-8750] SANYO : DIP30S (400 mil) Block Diagram LC7185-8750 Pin Assignment No. 3356-3/12 ...
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... CH19 Emergency CH19 recall PA Public announcement display MODE 1/2 Display Mode UP CH up/scan DN CH down/scan LED Display Configuration (Common anode/7 segment) LC7185-8750 PD Charge pump output NC NC pin Segment driver (for display) D1, D2 Digit output (for display) KI1 to KI4 Key inputs KO1 to KO3 ...
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... UL 18 BEEP LC7185-8750 Type . Transmit/receive select TX = ‘‘0’’...Transmit ‘‘1’’...Receive . Hold mode select HOLD = ‘‘0’’...Hold mode select = ‘‘1’’...Normal mode select . Reset line INIT = ‘ ...
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... The UL line is asserted for 25 ms after the CH9 or CH19 switch is turned off or on. 7. Causes either ‘‘9’’ or ‘‘19’’ to blink on the display. CH9/CH19 Switch Channel LC7185-8750 Type . Key inputs Input from the key matrix . Key scan output (75 Hz) ...
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... Example: Display 21 → 15 key M1 Mode 2 (with diode) Each time a key is pressed (M1 to M5), a key mnemonic (‘‘P1’’ to ‘‘P5’’) is displayed for 400 ms, then the new channel is displayed. Example: Display 21 → P1 → 15 Key M1 LC7185-8750 Lock: Open 400 ms No. 3356-7/12 ...
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... After a new transmit/receive or channel selection, the UL line is asserted for 25 ms While the PA switch is turned on, the UL line is asserted during PA mode. The UL pin is open while the device is in the PLL LOCK state (when the phase difference is < 3.2 µs). LC7185-8750 → 400 ms M1 ...
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... When the LC7185-8750 leaves hold mode, the previously selected channel is reopened. (2) Initial state settings The LC7185-8750 can be reset to its initial state settings (reset) after the battery has been replaced, etc., by setting INIT = 0. The initial state that is established by an initial reset is as follows: ...
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... DD There are no constraints on timing for the HOLD and V The signal can be activated in one of two orders. If HOLD is already deactivated (> 0 > 5.0 V, the LC7185-8750 enters normal mode within 2.0 ms after HOLD is deactivated. DD (4) Reset Timing 1. Reset timing (e.g. battery replacement) Note: tINIT should be greater than 1.0 µs. ...
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... Frequency Table (U.S.A.: LC7185-8750) FREQUENCY CHANNEL (MHz) 1 26.965 2 26.975 3 26.985 4 27.005 5 27.015 6 27.025 7 27.035 8 27.055 9 27.065 10 27.075 11 27.085 12 27.105 13 27.115 14 27.125 15 27.135 16 27.155 17 27.165 18 27.175 19 27.185 20 27.205 21 27.215 22 27.225 23 27.255 24 27.235 25 27.245 26 27.265 27 27.275 28 27.285 29 27.295 30 27.305 31 27.315 32 27.325 33 27.335 34 27.345 35 27.355 36 27 ...
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... SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 2006. Specifications and information herein are subject to change without notice. LC7185-8750 PS No. 3356-12/12 ...