MC100EPT22DT ON Semiconductor, MC100EPT22DT Datasheet

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MC100EPT22DT

Manufacturer Part Number
MC100EPT22DT
Description
Manufacturer
ON Semiconductor
Datasheet

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MC100EPT22
3.3V Dual LVTTL/LVCMOS
to Differential LVPECL
Translator
Description
LVPECL translator. Because LVPECL (Positive ECL) levels are used
only +3.3 V and ground are required. The small outline 8−lead
package and the single gate of the EPT22 makes it ideal for those
applications where space, performance, and low power are at a
premium. Because the mature MOSAIC 5 process is used, low cost
and high speed can be added to the list of features.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 12
The MC100EPT22 is a dual LVTTL/LVCMOS to differential
420 ps Typical Propagation Delay
Maximum Frequency > 1.1 GHz Typical
Operating Range: V
PNP LVTTL Inputs for Minimal Loading
Q Output Will Default HIGH with Inputs Open
The 100 Series Contains Temperature Compensation.
Pb−Free Packages are Available
CC
= 3.0 V to 3.6 V with GND = 0 V
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional marking information, refer to
8
(Note: Microdot may be in either location)
Application Note AND8002/D.
8
ORDERING INFORMATION
1
1
A
L
Y
W
M
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
CASE 506AA
CASE 751
D SUFFIX
MN SUFFIX
CASE 948R
SOIC−8
DT SUFFIX
TSSOP−8
DFN8
Publication Order Number:
MC100EPT22/D
DIAGRAMS*
8
1
MARKING
8
1
KPT22
ALYW
ALYWG
1
KA22
G
G
4

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MC100EPT22DT Summary of contents

Page 1

MC100EPT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Description The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The small outline 8−lead package and the single ...

Page 2

LVPECL LVTTL Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V Power Supply CC V Input Voltage I I Output Current out T Operating Temperature Range A T Storage Temperature Range stg Thermal Resistance (Junction−to−Ambient Thermal Resistance (Junction−to−Case Thermal ...

Page 4

Table 6. AC CHARACTERISTICS V Symbol Characteristic f Maximum Frequency (Figure 2) max t , Propagation Delay to PLH t Output Differential PHL t Within−Device Skew (Note 6) skew Device−to−Device Skew (Note 7) t Random Clock Jitter (Figure 2) JITTER ...

Page 5

... ORDERING INFORMATION Device MC100EPT22D MC100EPT22DG MC100EPT22DR2 MC100EPT22DR2G MC100EPT22DT MC100EPT22DTG MC100EPT22DTR2 MC100EPT22DTR2G MC100EPT22MNR4 MC100EPT22MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D ...

Page 6

... C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004) ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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