MX25L6405DMI-12G Macronix International Co., MX25L6405DMI-12G Datasheet
MX25L6405DMI-12G
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MX25L6405DMI-12G Summary of contents
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FEATURES GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure 32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two ...
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Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - Both REMS and REMS2 commands for 1-byte manufacturer ID and 1-byte device ID HARDWARE FEATURES • ...
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To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced ...
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PIN CONFIGURATIONS 16-PIN SOP (300mil) 1 HOLD# SCLK 16 VCC 2 SI/SIO0 CS# 7 GND 10 SO/SIO1 8 WP#/ACC 9 8-LAND WSON (8x6mm, ...
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BLOCK DIAGRAM SI/SIO0 SO/SIO1 CS#, WP#/ACC, HOLD# SCLK P/N: PM1290 Address Generator Memory Array Page Buffer Data Register SRAM Buffer Mode State Logic Machine Generator Clock Generator 5 MX25L1605D MX25L3205D MX25L6405D Y-Decoder Sense Amplifier HV Output Buffer REV. 1.4, OCT. ...
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DATA PROTECTION The MX25L1605D/3205D/6405D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. ...
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Table 2. Protected Area Sizes Status bit BP3 BP2 BP1 BP0 16Mb 0(none 1(1block, block 31th 2(2blocks, block 30th-31th 3(4blocks, block 28th-31th ...
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HOLD FEATURES HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping ...
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Table 4. COMMAND DEFINITION COMMAND WREN WRDI RDID (read (byte) (write (write identification enable) disable) ) 1st byte 06 (hex) 04 (hex) 9F (hex) 2nd byte 3rd byte 4th byte 5th byte Action sets the resets the outputs (WEL) (WEL) ...
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Table 5-1. Memory Organization (16Mb) Address Range Block Sector 511 1FF000h 1FFFFFh . . . . 496 1F0000h 1F0FFFh 495 1EF000h 1EFFFFh . . . . 480 1E0000h 1E0FFFh 479 1DF000h 1DFFFFh . . ...
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Table 5-2. Memory Organization (32Mb) Address Range Block Sector 1023 3FF000h 3FFFFFh . . . . 1008 3F0000h 3F0FFFh 1007 3EF000h 3EFFFFh . . . . 992 3E0000h 3E0FFFh 991 3DF000h 3DFFFFh . . ...
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Address Range Block Sector 511 1FF000h 1FFFFFh . . . . 496 1F0000h 1F0FFFh 495 1EF000h 1EFFFFh . . . . 480 1E0000h 1E0FFFh 479 1DF000h 1DFFFFh . . . . ...
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Table 5-3. Memory Organization (64Mb) Address Range Block Sector 2047 7FF000h 7FFFFFh . . . . 127 . . 2032 7F0000h 2031 7EF000h 7EFFFFh . . . . 126 . . 2016 7E0000h 7E0FFFh 2015 7DF000h 7DFFFFh . . . ...
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Address Range Block Sector 1535 5FF000h . . . . 1520 5F0000h 1519 5EF000h . . . . 1504 5E0000h 1503 5DF000h . . . . 1488 5D0000h 1487 5CF000h . ...
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Address Range Block Sector 1023 3FF000h 3FFFFFh . . . . 1008 3F0000h 3F0FFFh 1007 3EF000h 3EFFFFh . . . . 992 3E0000h 3E0FFFh 991 3DF000h 3DFFFFh . . . . ...
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Address Range Block Sector 511 1FF000h 1FFFFFh . . . . 496 1F0000h 495 1EF000h 1EFFFFh . . . . 480 1E0000h 1E0FFFh 479 1DF000h 1DFFFFh . . . . 464 ...
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DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby ...
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COMMAND DESCRIPTION (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, CP, SE, BE, CE, and WRSR, which are intended to change the device content, should be ...
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Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously recommended to check the Write in ...
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Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ...
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Note: If SRWD bit=1 but WP#/ACC is low impossible to write the Status Register even if the WEL bit has previously been set rejected to write the Status Register and not be executed. Hardware Protected Mode ...
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While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. The 2 I/O only perform read operation. Program/Erase /Read ID/Read status/Read ID....operation do not support 2 I/O throughputs. ...
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The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 ...
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Software method-II: by waiting for a tBP time out to determine if it may load next valid command or not. 3) Hardware method: by writing ESRY (enable SO to output RY/BY#) instruction to detect the completion of a program ...
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Read Electronic Manufacturer ID & Device ID (REMS), (REMS2) The REMS & REMS2 instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The REMS ...
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Read Security Register (RDSCUR) The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. The sequence of ...
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POWER-ON STATE The device is at below states when power-up: - Standby mode ( please note it is not deep power-down mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential NOTICE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This ...
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Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing referance level 0.8VCC 0.2VCC Figure 7. OUTPUT LOADING DEVICE UNDER TEST P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and ...
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Table 9. DC CHARACTERISTICS (Temperature = -40° ° ° ° ° 85° ° ° ° ° C for Industrial grade, VCC = 2.7V ~ 3.6V) SYMBOL PARAMETER NOTES ILI Input Load Current ILO Output Leakage Current ILIHV HV ...
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Table 10. AC CHARACTERISTICS (Temperature = -40° ° ° ° ° 85° ° ° ° ° C for Industrial grade, VCC = 2.7V ~ 3.6V) Symbol Alt. Parameter fSCLK fC Clock Frequency for the following instructions: FAST_READ, PP, ...
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Symbol Alt. Parameter tW Write Status Register Cycle Time tBP Byte-Program tPP Page Program Cycle Time tSE Sector Erase Cycle Time tBE Block Erase Cycle Time tCE Chip Erase Cycle Time Notes: 1. tCH + tCL must be greater than ...
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Table 11. Power-Up Timing and VWI Threshold Symbol Parameter tVSL(1) VCC(min) to CS# low tPUW(1) Time delay to Write instruction VWI(1) Write Inhibit Voltage Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the ...
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Figure 8. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 9. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1290 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 34 MX25L1605D ...
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Figure 10. Hold Timing CS# SCLK SO HOLD "don't care" during HOLD operation. Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tWHSL CS SCLK SI High-Z SO P/N: PM1290 tHLCH ...
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Figure 12. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 13. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO Figure 14. Read Identification (RDID) Sequence (Command 9F) CS SCLK Command SI High-Z ...
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Figure 15. Read Status Register (RDSR) Sequence (Command 05) CS SCLK command SI High-Z SO Figure 16. Write Status Register (WRSR) Sequence (Command 01) CS# SCLK SI SO Figure 17. Read Data Bytes (READ) Sequence (Command 03) ...
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Figure 18. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS SCLK Command SI 0B High SCLK Dummy Byte P/N: PM1290 ...
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Figure 19 I/O Read Mode Sequence (Command BB) CS SCLK BB(hex) SI/SIO0 High Impedance SO/SIO1 Figure 20. Page Program (PP) Sequence (Command 02) CS SCLK Command SI CS# 40 ...
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Figure 21. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD) CS SCLK Command SI AD (hex) 24-bit address high impedance S0 Note: (1) During CP mode, the valid commands are CP command ...
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Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) CS# SCLK SI Note: CE command is 60(hex) or C7(hex). Figure 25. Deep Power-down (DP) Sequence (Command B9) CS SCLK SI Figure 26. Release from Deep Power-down and ...
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Figure 27. Release from Deep Power-down (RDP) Sequence (Command AB) CS SCLK SI High-Z SO Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF) CS SCLK Command SI 90 ...
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Figure 29. Power-up Timing (max) Program, Erase and Write Commands are Ignored V CC (min) Reset State of the Flash V WI Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V. P/N: PM1290 Chip Selection ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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ERASE AND PROGRAMMING PERFORMANCE PARAMETER Write Status Register Cycle Time Sector Erase Time Block Erase Time Chip Erase Time Chip Erase Time (at ACC mode) Byte Program Time (via page program command) Page Program Time Page Program Time (at ACC ...
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... MX25L1605DM2I-12G 86 MX25L1605DMI-12G 86 MX25L1605DM1I-12G 86 MX25L1605DPI-12G 86 MX25L1605DZNI-12G 86 MX25L1605DZUI-12G 86 MX25L3205DZNI-12G 86 MX25L3205DM2I-12G 86 MX25L3205DMI-12G 86 MX25L3205DPI-12G 86 MX25L3205DZUI-12G 86 MX25L6405DZNI-12G 86 MX25L6405DMI-12G 86 P/N: PM1290 OPERATING STANDBY Temperature PACKAGE Remark CURRENT MAX. CURRENT MAX. (mA) (uA -40° C~85° C 8-SOP 25 20 -40°C~85° -40°C~85° -40°C~85° -40°C~85° -40° ...
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PART NAME DESCRIPTION 1605D P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D OPTION: G: Pb-free SPEED: 12: 86MHz TEMPERATURE RANGE: I: Industrial (-40˚C to 85˚C) PACKAGE: ZN: WSON (0.8mm package height) ZU: USON (0.6mm package height) ...
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PACKAGE INFORMATION P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D 48 REV. 1.4, OCT. 01, 2008 ...
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P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D 49 REV. 1.4, OCT. 01, 2008 ...
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P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D 50 REV. 1.4, OCT. 01, 2008 ...
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P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D 51 REV. 1.4, OCT. 01, 2008 ...
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P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D 52 REV. 1.4, OCT. 01, 2008 ...
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P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D 53 REV. 1.4, OCT. 01, 2008 ...
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P/N: PM1290 MX25L1605D MX25L3205D MX25L6405D 54 REV. 1.4, OCT. 01, 2008 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 1.1 1. Dual I/O Pre-released 1.2 1. Added 8-land USON package information 1.3 1. Modified figure 4 & 5 waveform 2. Revised VHH spec from 11.0V(typ.)~11.5V(max.) to 9.5V(min.)~10.5V(max.) 1.4 1. Revised ...
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... Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Singapore Office Macronix Pte. Ltd. 1 Marine Parade Central #11-03 Parkway Centre Singapore 449408 Tel: +65-6346-5505 Fax: +65-6348-8096 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 56 MX25L1605D MX25L3205D MX25L6405D ...