PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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Page 109/202

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10.4.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART. If the RX/DT or TX/CK pins are shared with an
analog peripheral the analog I/O functions must be
disabled by clearing the corresponding ANSEL bits.
10.4.2.1
EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and Slave
modes
are
identical
(see
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 10-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
BAUDCTL ABDOVF
RCIDL
INTCON
GIE
PEIE
T0IE
PIE1
EEIE
ADIE
RCIE
PIR1
EEIF
ADIF
RCIF
RCREG
EUSART Receive Data Register
RCSTA
SPEN
RX9
SREN
SPBRG
BRG7
BRG6
BRG5
SPBRGH
BRG15
BRG14
BRG13
TRISC
TRISC5
TXREG
EUSART Transmit Data Register
TXSTA
CSRC
TX9
TXEN
Legend:
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
© 2007 Microchip Technology Inc.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
The first character will immediately transfer to
the TSR register and transmit.
2.
The second word will remain in TXREG register.
3.
The TXIF bit will not be set.
4.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
5.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
10.4.2.2
1.
Set the SYNC and SPEN bits and clear the
CSRC bit.
2.
Clear the CREN and SREN bits.
3.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
TXIE bit.
Section 10.4.1.3
4.
If 9-bit transmission is desired, set the TX9 bit.
5.
Enable transmission by setting the TXEN bit.
6.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
7.
Start
transmission
Significant 8 bits to the TXREG register.
Bit 4
Bit 3
Bit 2
Bit 1
SCKP
BRG16
WUE
INTE
RAIE
T0IF
INTF
C2IE
C1IE
OSFIE
TXIE
C2IF
C1IF
OSFIF
TXIF
CREN
ADDEN
FERR
OERR
BRG4
BRG3
BRG2
BRG1
BRG12
BRG11
BRG10
BRG9
TRISC4
TRISC3
TRISC2
TRISC1
SYNC
SENDB
BRGH
TRMT
PIC16F688
Synchronous Slave Transmission
Set-up:
by
writing
the
Least
Value on
Value on
Bit 0
all other
POR, BOR
Resets
ABDEN
01-0 0-00
01-0 0-00
RAIF
0000 000x
0000 000x
0000 0000
0000 0000
TMR1IE
0000 0000
0000 0000
TMR1IF
0000 0000
0000 0000
RX9D
0000 000x
0000 000x
BRG0
0000 0000
0000 0000
BRG8
0000 0000
0000 0000
--11 1111
TRISC0
--11 1111
0000 0000
0000 0000
TX9D
0000 0010
0000 0010
DS41203D-page 107