PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 


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PIC16F688
10.1.2.8
Asynchronous Reception Set-up:
1.
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 10.3 “EUSART
Baud Rate Generator (BRG)”).
2.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
4.
If 9-bit reception is desired, set the RX9 bit.
5.
Enable reception by setting the CREN bit.
6.
The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
7.
Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
8.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
9.
If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
Start
bit
RX/DT pin
bit 0
bit 1
Rcv Shift
Reg
Rcv Buffer Reg
RCIDL
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41203D-page 90
10.1.2.9
9-bit Address Detection Mode Set-up
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
Initialize the SPBRGH, SPBRG register pair and
the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 10.3 “EUSART
Baud Rate Generator (BRG)”).
2.
Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
3.
If interrupts are desired, set the RCIE interrupt
enable bit and set the GIE and PEIE bits of the
INTCON register.
4.
Enable 9-bit reception by setting the RX9 bit.
5.
Enable address detection by setting the ADDEN
bit.
6.
Enable reception by setting the CREN bit.
7.
The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
8.
Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
9.
Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
Start
bit 7/8
bit 7/8 Stop
Stop
bit
bit 0
bit
bit
Word 2
Word 1
RCREG
RCREG
Start
bit
Stop
bit 7/8
bit
© 2007 Microchip Technology Inc.