PIC16F688

Manufacturer Part NumberPIC16F688
ManufacturerMicrochip Technology Inc.
PIC16F688 datasheet
 
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Page 97/202:

EUSART Baud Rate Generator

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10.3

EUSART Baud Rate Generator

(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCTL register selects 16-bit
mode.
The SPBRGH, SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCTL register. In
Synchronous mode, the BRGH bit is ignored.
Table 10-3 contains the formulas for determining the
baud rate. Example 10-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 10-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
TABLE 10-3:
BAUD RATE FORMULAS
Configuration Bits
SYNC
BRG16
BRGH
0
0
0
0
0
1
0
1
0
0
1
1
1
0
x
1
1
x
Legend:
x = Don’t care, n = value of SPBRGH, SPBRG register pair
TABLE 10-4:
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
BAUDCTL ABDOVF
RCIDL
RCSTA
SPEN
RX9
SREN
SPBRG
BRG7
BRG6
BRG5
SPBRGH
BRG15
BRG14
BRG13
TXSTA
CSRC
TX9
TXEN
Legend:
x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
© 2007 Microchip Technology Inc.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 10-1:
For a device with F
of 9600, Asynchronous mode, 8-bit BRG:
Desired Baud Rate
Solving for SPBRGH:SPBRG:
Calculated Baud Rate
Error
BRG/EUSART Mode
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
Bit 4
Bit 3
Bit 2
Bit 1
SCKP
BRG16
WUE
CREN
ADDEN
FERR
OERR
BRG4
BRG3
BRG2
BRG1
BRG12
BRG11
BRG10
BRG9
SYNC
SENDB
BRGH
TRMT
PIC16F688
CALCULATING BAUD
RATE ERROR
of 16 MHz, desired baud rate
OSC
F
OS C
-------------------------------------------------------------------- -
=
(
)
64 [SPBRGH:SPBRG]
+
1
F
O S C
-------------------------------------------- -
Desired Baud Rate
--------------------------------------------- 1
X
=
64
16000000
----------------------- -
9600
----------------------- - 1
=
64
[
]
=
25.042
=
25
16000000
-------------------------- -
=
(
)
64 25
+
1
=
9615
Calc. Baud Rate Desired Baud Rate
------------------------------------------------------------------------------------------- -
=
Desired Baud Rate
(
)
9615 9600
----------------------------------
=
=
0.16%
9600
Baud Rate Formula
F
/[64 (n+1)]
OSC
F
/[16 (n+1)]
OSC
F
/[4 (n+1)]
OSC
Value on
Value on
Bit 0
all other
POR, BOR
Resets
ABDEN
01-0 0-00
01-0 0-00
RX9D
0000 000x
0000 000x
BRG0
0000 0000
0000 0000
BRG8
0000 0000
0000 0000
TX9D
0000 0010
0000 0010
DS41203D-page 95