PIC18F87J50 Microchip Technology Inc., PIC18F87J50 Datasheet
PIC18F87J50
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PIC18F87J50 Summary of contents
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... Flash USB Microcontrollers © 2007 Microchip Technology Inc. PIC18F87J50 Family Data Sheet 64/80-Pin High-Performance, with nanoWatt Technology Preliminary DS39775B ...
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... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , K L logo, microID, MPLAB, PIC DSCs code hopping ® ® © 2007 Microchip Technology Inc. ...
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... C™ Master and Slave modes • 8-Bit Parallel Master Port/Enhanced Parallel Slave Port with 16 Address Lines • Dual Analog Comparators with Input Multiplexing © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Peripheral Highlights (continued): • 10-Bit 12-Channel Analog-to-Digital (A/D) Converter module: - Auto-acquisition capability - Conversion available during Sleep • ...
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... PIC18F87J50 FAMILY SRAM Data Flash Program Device Memory Memory (bytes) (bytes) PIC18F65J50 32K 3904* PIC18F66J50 64K 3904* PIC18F66J55 96K 3904* PIC18F67J50 128K 3904* PIC18F85J50 32K 3904* PIC18F86J50 64K 3904* PIC18F86J55 96K 3904* PIC18F87J50 128K 3904* * Includes the dual access RAM used by the USB module which is shared with data memory. ...
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... The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. 3: PMP pin placement when PMPMX = 1. 4: PMP pin placement when PMPMX = 0. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY PIC18F8XJ5X Preliminary RJ2/WRL 60 RJ3/WRH 59 RB0/FLT0/INT0 ...
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... PIC18F87J50 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 33 3.0 Power-Managed Modes ............................................................................................................................................................. 45 4.0 Reset .......................................................................................................................................................................................... 53 5.0 Memory Organization ................................................................................................................................................................. 67 6.0 Flash Program Memory .............................................................................................................................................................. 95 7.0 External Memory Bus ............................................................................................................................................................... 105 8 Hardware Multiplier.......................................................................................................................................................... 117 9.0 Interrupts .................................................................................................................................................................................. 119 10.0 I/O Ports ................................................................................................................................................................................... 135 11.0 Parallel Master Port .................................................................................................................................................................. 165 12.0 Timer0 Module ......................................................................................................................................................................... 189 13.0 Timer1 Module ......................................................................................................................................................................... 193 14.0 Timer2 Module ......................................................................................................................................................................... 199 15 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Preliminary DS39775B-page 5 ...
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... PIC18F87J50 FAMILY NOTES: DS39775B-page 6 Preliminary © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F87J50 FAMILY 1.1.3 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F87J50 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. ...
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... This is true when moving between the 64-pin members, between the 80-pin members, or even jumping from 64-pin to 80-pin devices. The PIC18F87J50 family is also pin compatible with other PIC18 families, such as the PIC18F87J10, PIC18F87J11, PIC18F8720 and PIC18F8722. This allows a new dimension to the evolution of applications, allowing developers to select different price points within Microchip’ ...
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... Timers Capture/Compare/PWM Modules Enhanced Capture/ Compare/PWM Modules Serial Communications Parallel Communications (PMP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY PIC18F65J50 PIC18F66J50 DC – 48 MHz DC – 48 MHz 32K 64K 16384 32768 3904 3904 ...
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... PIC18F87J50 FAMILY FIGURE 1-1: PIC18F6XJ5X (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (32-128 Kbytes) Data Latch 8 Instruction Bus <16> Timing Generation OSC2/CLKO OSC1/CLKI 8 MHz INTOSC INTRC Oscillator V USB USB Module Precision Band Gap Reference ENVREG Voltage Regulator V /V DDCORE ...
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... Timer0 10-Bit PMP ECCP1 ECCP2 ECCP3 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Data Latch 8 8 Data Memory (3.9 Kbytes) PCLATU PCLATH Address Latch 20 PCU PCH ...
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... PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS Pin Number Pin Name 64-TQFP MCLR 7 OSC1/CLKI/RA7 39 OSC1 CLKI (3) RA7 OSC2/CLKO/RA6 40 OSC2 CLKO (3) RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-TQFP RB0/FLT0/INT0 48 RB0 FLT0 INT0 RB1/INT1/PMA4 47 RB1 INT1 PMA4 RB2/INT2/PMA3 46 RB2 INT2 PMA3 RB3/INT3/PMA2 45 RB3 INT3 PMA2 RB4/KBI0/PMA1 44 RB4 KBI0 PMA1 RB5/KBI1/PMA0 43 RB5 KBI1 PMA0 RB6/KBI2/PGC 42 RB6 KBI2 PGC RB7/KBI3/PGD ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-TQFP RD0/PMD0 58 RD0 PMD0 RD1/PMD1 55 RD1 PMD1 RD2/PMD2 54 RD2 PMD2 RD3/PMD3 53 RD3 PMD3 RD4/PMD4/SDO2 52 RD4 PMD4 SDO2 RD5/PMD5/SDI2/SDA2 51 RD5 PMD5 SDI2 SDA2 RD6/PMD6/SCK2/SCL2 50 RD6 PMD6 SCK2 SCL2 RD7/PMD7/SS2 49 RD7 PMD7 ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... PIC18F87J50 FAMILY TABLE 1-3: PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-TQFP RF2/PMA5/AN7/C2INB 16 RF2 PMA5 AN7 C2INB RF3/D- 15 RF3 D- RF4/D+ 14 RF4 D+ RF5/AN10/C1INB/CV 13 REF RF5 AN10 C1INB CV REF RF6/AN11/C1INA 12 RF6 AN11 C1INA RF7/SS1/C1OUT 11 RF7 SS1 C1OUT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS Pin Number Pin Name 80-TQFP MCLR 9 OSC1/CLKI/RA7 49 OSC1 CLKI (8) RA7 OSC2/CLKO/RA6 50 OSC2 CLKO (8) RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller mode) ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O ...
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... PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RB0/FLT0/INT0 58 RB0 FLT0 INT0 RB1/INT1/PMA4 57 RB1 INT1 PMA4 RB2/INT2/PMA3 56 RB2 INT2 PMA3 RB3/INT3/ECCP2/ 55 P2A/PMA2 RB3 INT3 (1) ECCP2 (1) P2A PMA2 RB4/KBI0/PMA1 54 RB4 KBI0 PMA1 RB5/KBI1/PMA0 53 RB5 KBI1 PMA0 RB6/KBI2/PGC 52 RB6 ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RD0/AD0/PMD0 72 RD0 AD0 (6) PMD0 RD1/AD1/PMD1 69 RD1 AD1 (6) PMD1 RD2/AD2/PMD2 68 RD2 AD2 (6) PMD2 RD3/AD3/PMD3 67 RD3 AD3 (6) PMD3 RD4/AD4/PMD4/ 66 SDO2 RD4 AD4 (6) PMD4 SDO2 RD5/AD5/PMD5/ 65 SDI2/SDA2 RD5 AD5 (6) PMD5 SDI2 SDA2 ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port (continued). I/O ST Digital I/O ...
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... PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RE0/AD8/PMRD/P2D 4 RE0 AD8 (6) PMRD P2D RE1/AD9/PMWR/P2C 3 RE1 AD9 (6) PMWR P2C RE2/AD10/PMBE/P2B 78 RE2 AD10 (6) PMBE P2B RE3/AD11/PMA13/ 77 P3C/REFO RE3 AD11 PMA13 (3) P3C REFO RE4/AD12/PMA12/P3B 76 RE4 AD12 PMA12 (3) P3B RE5/AD13/PMA11/P1C 75 RE5 ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port (continued). I/O ST Digital I/O ...
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... PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RF2/PMA5/AN7/C2INB 18 RF2 PMA5 AN7 C2INB RF3/D- 17 RF3 D- RF4/D+ 16 RF4 D+ RF5/PMD2/AN10/ 15 C1INB/CV REF RF5 (7) PMD2 AN10 C1INB CV REF RF6/PMD1/AN11/C1INA 14 RF6 (7) PMD1 AN11 C1INA RF7/PMD0/SS1/C1OUT 13 RF7 (7) PMD0 SS1 C1OUT Legend: TTL = TTL compatible input ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RH0/A16 79 RH0 A16 RH1/A17 80 RH1 A17 RH2/A18/PMD7 1 RH2 A18 (7) PMD7 RH3/A19/PMD6 2 RH3 A19 (7) PMD6 RH4/PMD3/AN12/ 22 P3C/C2INC RH4 (7) PMD3 AN12 (5) P3C C2INC RH5/PMBE/AN13/ 21 P3B/C2IND RH5 (7) PMBE AN13 (5) P3B C2IND RH6/PMRD/AN14/ ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port (continued). I/O ST Digital I/O ...
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... PIC18F87J50 FAMILY TABLE 1-4: PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 80-TQFP RJ0/ALE 62 RJ0 ALE RJ1/OE 61 RJ1 OE RJ2/WRL 60 RJ2 WRL RJ3/WRH 59 RJ3 WRH RJ4/BA0 39 RJ4 BA0 RJ5/CE 40 RJ5 CE RJ6/LB 41 RJ6 LB RJ7/UB 42 RJ7 UB V 11, 31, 51 32, 48 ...
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... PLL. Its use is described in Section 2.2.5.1 “OSCTUNE Register”. 2.2 Oscillator Types PIC18F87J50 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC2:FOSC0 Configuration bits to select one of the modes listed in Table 2-1. For oscillator modes which produce a clock output, “CLKO”, on pin RA6, the output frequency will be one fourth of the peripheral clock frequency ...
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... The USB module cannot be used to communicate unless the primary clock source is selected. DS39775B-page 34 A network of MUXes, clock dividers and a fixed 96 MHz output PLL have been provided which can be used to derive various microcontroller core and USB module frequencies. PIC18F87J50 family of devices is best understood by referring to Figure 2-1. PLLDIV2:PLLDIV0 ÷ 12 000 ÷ 10 001 ÷ ...
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... See the notes following Table 2-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY TABLE 2-3: Osc Type HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...
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... F /4 OSC 2.2.4 PLL FREQUENCY MULTIPLIER PIC18F87J50 family devices include a Phase Locked Loop (PLL) circuit. This is provided specifically for USB applications with lower speed oscillators and can also be used as a microcontroller clock source. The PLL can be enabled in HSPLL, ECPLL, INTOSCPLL and INTOSCPLLO Oscillator modes by setting the PLLEN bit (OSCTUNE< ...
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... INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 2.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency ...
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... Minimum frequency 2.3 Oscillator Settings for USB When the PIC18F87J50 family is used for USB connectivity MHz or 48 MHz clock must be provided to the USB module for operation in either Low-Speed or Full-Speed modes, respectively. This may require some forethought in selecting an oscillator frequency and programming the device ...
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... Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Note 1: Only valid for low-speed USB operation. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Clock Mode MCU Clock Division (FOSC2:FOSC0) (CPDIV1:CPDIV0) None (11) ÷ ...
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... Switching Like previous PIC18 enhanced PIC18F87J50 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F87J50 family devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available ...
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... Microchip Technology Inc. PIC18F87J50 FAMILY 2.4.2 OSCILLATOR TRANSITIONS PIC18F87J50 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F87J50 FAMILY REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-1 IDLEN IRCF2 IRCF1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits ...
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... Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F87J50 family can also be configured to provide a reference clock output signal to a port pin. This feature is avail- able in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application ...
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... PIC18F87J50 FAMILY 2.6 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. Unless the USB module is enabled, the OSC1 pin (and OSC2 pin if used by the oscillator) will stop oscillating ...
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... POWER-MANAGED MODES The PIC18F87J50 family devices provide the ability to manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F87J50 FAMILY 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its ...
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... These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
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... PIC18F87J50 FAMILY 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times ...
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... These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... PIC18F87J50 FAMILY 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J50 FAMILY NOTES: DS39775B-page 52 Preliminary © 2007 Microchip Technology Inc. ...
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... RESET The PIC18F87J50 family of devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset i) Stack Underflow Reset ...
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... PIC18F87J50 FAMILY REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 R/W-1 IPEN — CM bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 Unimplemented: Read as ‘0’ ...
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... POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any Power-on Reset. 4.4 Brown-out Reset (BOR) The PIC18F87J50 family of devices incorporates a simple BOR function when the internal regulator is enabled (ENVREG pin is tied Any drop ...
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... Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87J50 fam- ily devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μ ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY T PWRT , V RISE > 3. PWRT Preliminary ): CASE ...
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... PIC18F87J50 FAMILY 4.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction Brown-out Reset Stack Resets ...
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... PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F6XJ5X PIC18F8XJ5X POSTINC2 PIC18F6XJ5X PIC18F8XJ5X POSTDEC2 PIC18F6XJ5X PIC18F8XJ5X PREINC2 PIC18F6XJ5X PIC18F8XJ5X PLUSW2 PIC18F6XJ5X PIC18F8XJ5X FSR2H PIC18F6XJ5X PIC18F8XJ5X FSR2L PIC18F6XJ5X PIC18F8XJ5X STATUS PIC18F6XJ5X PIC18F8XJ5X TMR0H PIC18F6XJ5X PIC18F8XJ5X TMR0L PIC18F6XJ5X ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction Brown-out Reset Stack Resets ...
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... PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices IPR3 PIC18F6XJ5X PIC18F8XJ5X PIR3 PIC18F6XJ5X PIC18F8XJ5X PIE3 PIC18F6XJ5X PIC18F8XJ5X IPR2 PIC18F6XJ5X PIC18F8XJ5X PIR2 PIC18F6XJ5X PIC18F8XJ5X PIE2 PIC18F6XJ5X PIC18F8XJ5X IPR1 PIC18F6XJ5X PIC18F8XJ5X PIR1 PIC18F6XJ5X PIC18F8XJ5X PIE1 PIC18F6XJ5X PIC18F8XJ5X RCSTA2 PIC18F6XJ5X ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction Brown-out Reset Stack Resets ...
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... PIC18F87J50 FAMILY TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PMADDRH PIC18F6XJ5X PIC18F8XJ5X PMDOUT1H PIC18F6XJ5X PIC18F8XJ5X PMADDRL PIC18F6XJ5X PIC18F8XJ5X PMDOUT1L PIC18F6XJ5X PIC18F8XJ5X PMDIN1H PIC18F6XJ5X PIC18F8XJ5X PMDIN1L PIC18F6XJ5X PIC18F8XJ5X UCON PIC18F6XJ5X PIC18F8XJ5X USTAT PIC18F6XJ5X PIC18F8XJ5X UEIR PIC18F6XJ5X PIC18F8XJ5X UIR PIC18F6XJ5X ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction Brown-out Reset Stack Resets ...
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... PIC18F87J50 FAMILY NOTES: DS39775B-page 66 Preliminary © 2007 Microchip Technology Inc. ...
Page 69
... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F87J50 family offers a range of on-chip Flash program memory sizes, from 64 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 ...
Page 70
... Configuration Words, CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices in the PIC18F87J50 family are shown in Table 5-1. Their location in the memory map is shown with the other memory vectors in Figure 5-2. Additional details on the device Configuration Words are provided in Section 25.1 “Configuration Bits”. ...
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... PIC18F87J50 FAMILY PROGRAM MEMORY MODES The 80-pin devices in this family can address total of 2 Mbytes of program memory. This is achieved through the External Memory Bus. There are two distinct operating modes available to the controllers: • Microcontroller (MC) • Extended Microcontroller (EMC) The program memory mode is determined by setting the EMB Configuration bits (CONFIG3L< ...
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... In practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 5-3: MEMORY MAPS FOR PIC18F87J50 FAMILY PROGRAM MEMORY MODES (1) Microcontroller Mode Extended Microcontroller Mode On-Chip ...
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... Microchip Technology Inc. PIC18F87J50 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... PIC18F87J50 FAMILY 5.1.6.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F87J50 FAMILY 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruc- tion Register (IR) during Q4 ...
Page 77
... ADDWF © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... The memory space is divided into as many as 16 banks that contain 256 bytes each. The PIC18F87J50 family implements all available banks and provides 3904 bytes of data memory available to the user. Figure 5-7 shows the data memory organization for the devices ...
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... FIGURE 5-7: DATA MEMORY MAP FOR PIC18F87J50 FAMILY DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 FFh ...
Page 80
... PIC18F87J50 FAMILY FIGURE 5-8: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) (1) BSR (2) Bank Select Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 2: The MOVFF instruction embeds the entire 12-bit address in the instruction. ...
Page 81
... Resets and interrupts) and those related to the peripheral functions. The Reset and interrupt registers are described in their respective chapters, while the TABLE 5-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J50 FAMILY DEVICES Address Name Address Name ...
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... Since the bit remains in a given state until changed, users should always verify the state of ADSHR before writing to any of the shared SFR addresses. TABLE 5-4: SHARED SFR ADDRESSES FOR PIC18F87J50 FAMILY DEVICES Address Name FD3h (D) OSCCON ...
Page 83
... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) File Name Bit 7 Bit 6 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 FSR2L Indirect Data Memory Address Pointer 2 Low Byte STATUS — — TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS (2) OSCCON / IDLEN IRCF2 ...
Page 85
... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 ECCP1AS ECCP1ASE ECCP1AS2 ECCP1AS1 ECCP1AS0 ECCP1DEL P1RSEN P1DC6 P1DC5 CCPR1H Capture/Compare/PWM Register 1 HIgh Byte CCPR1L Capture/Compare/PWM Register 1 Low Byte CCP1CON P1M1 P1M0 DC1B1 ECCP2AS ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 ECCP2DEL P2RSEN ...
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... PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 (7) TRISJ TRISJ7 TRISJ6 TRISJ5 (7) TRISH TRISH7 TRISH6 TRISH5 TRISG — — TRISF TRISF7 TRISF6 TRISF5 TRISE TRISE7 TRISE6 TRISE5 TRISD TRISD7 TRISD6 TRISD5 TRISC TRISC7 TRISC6 TRISC5 ...
Page 87
... TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 CCPR4H Capture/Compare/PWM Register 4 High Byte CCPR4L Capture/Compare/PWM Register 4 Low Byte CCP4CON — — DC4B1 CCPR5H Capture/Compare/PWM Register 5 High Byte CCPR5L Capture/Compare/PWM Register 5 Low Byte CCP5CON — — DC5B1 SSP2BUF MSSP2 Receive Buffer/Transmit Register ...
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... PIC18F87J50 FAMILY TABLE 5-5: REGISTER FILE SUMMARY (PIC18F87J50 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 UEP7 — — UEP6 — — UEP5 — — UEP4 — — UEP3 — — UEP2 — — UEP1 — — UEP0 — — PMCONH PMPEN — PSIDL ...
Page 89
... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY register then reads back as ‘000u u1uu’ recom- mended, therefore, that only BCF, BSF, SWAPF, ...
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... PIC18F87J50 FAMILY 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
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... FCCh will be added to that of the W register and stored back in FCCh. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. ...
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... PIC18F87J50 FAMILY 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: • ...
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... The file address argument is less than or equal to 5Fh. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2 ...
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... PIC18F87J50 FAMILY FIGURE 5-10: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...
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... BSR. F60h FFFh © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F87J50 FAMILY NOTES: DS39775B-page 94 Preliminary © 2007 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes DD between the program memory space and the data RAM: • ...
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... PIC18F87J50 FAMILY FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
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... The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC18F87J50 FAMILY 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... MOVF TABLAT, W MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F87J50 FAMILY 6.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
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... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC of the PIC18F87J50 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten sequence. ...
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... PIC18F87J50 FAMILY EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE ...
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... FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PRORAMMING). The PIC18F87J50 family of devices have a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1. Load the Table Pointer register with the address of the data to be written ...
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... PIC18F87J50 FAMILY 6.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.4 UNEXPECTED TERMINATION OF WRITE OPERATION ...
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... The External Memory Bus (EMB) allows the device to access external memory devices (such as Flash, EPROM, SRAM, etc.) as program or data memory. It supports both 8 and 16-Bit Data Width modes and three address widths bits. TABLE 7-1: PIC18F87J50 FAMILY EXTERNAL BUS – I/O PORT FUNCTIONS Name Port RD0/AD0 PORTD RD1/AD1 ...
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... PIC18F87J50 FAMILY 7.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 7-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions ...
Page 109
... Address and Data Width The PIC18F87J50 family of devices can be indepen- dently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software ...
Page 110
... Program Memory Modes and the External Memory Bus The PIC18F87J50 family of devices is capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the EBDIS bit ...
Page 111
... BYTE WRITE MODE Figure 7-1 shows an example of 16-Bit Byte Write mode for PIC18F87J50 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories. ...
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... PIC18F87J50 FAMILY 7.6.2 16-BIT WORD WRITE MODE Figure 7-2 shows an example of 16-Bit Word Write mode for PIC18F87J50 family devices. This mode is used for word-wide memories which include some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
Page 113
... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 114
... PIC18F87J50 FAMILY 7.6.4 16-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 and Figure 7-5. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE A<19:16> AD<15:0> CE ALE ...
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... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY The Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available on the external memory interface bus. The Output Enable signal (OE) ...
Page 116
... PIC18F87J50 FAMILY 7.7.1 8-BIT MODE TIMING The presentation of control signals on the External Memory Bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-7 and Figure 7-8. FIGURE 7-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE A<19:16> AD<15:8> AD<7:0> CE ALE ...
Page 117
... Microchip Technology Inc. PIC18F87J50 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with ...
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... PIC18F87J50 FAMILY NOTES: DS39775B-page 116 Preliminary © 2007 Microchip Technology Inc. ...
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... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PIC18F87J50 FAMILY Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ...
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... INTERRUPTS Members of the PIC18F87J50 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
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... PIC18F87J50 FAMILY FIGURE 9-1: PIC18F87J50 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:0> PIE2<7:0> IPR2<7:0> PIR3<7:0> PIE3<7:0> IPR3<7:0> DS39775B-page 120 TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... PIC18F87J50 FAMILY REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 ...
Page 126
... PIC18F87J50 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 R-0 PMPIF ...
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... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 USBIF BCL1IF LVDIF U = Unimplemented bit, read as ‘0’ ...
Page 128
... PIC18F87J50 FAMILY REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software Waiting to transmit/receive ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ ...
Page 130
... PIC18F87J50 FAMILY REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 OSCFIE CM2IE CM1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CM2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 ...
Page 131
... CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 ...
Page 132
... PIC18F87J50 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 133
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-1 R/W-1 R/W-1 USBIP BCL1IP LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...
Page 134
... PIC18F87J50 FAMILY REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
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... PIC18F87J50 FAMILY 9.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
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... RD TRIS PORT © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
Page 138
... PIC18F87J50 FAMILY Table 10-2 summarizes the output capabilities of the ports. Refer to the “Absolute Maximum Ratings” in Section 28.0 “Electrical Characteristics” for more details. TABLE 10-2: OUTPUT DRIVE LEVELS Port Drive Description PORTA Minimum Intended for indication. PORTF PORTG (1) PORTH PORTD Medium Sufficient drive levels for ...
Page 139
... Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits 1 = Open-drain output on SDOx pin enabled 0 = Open-drain output disabled © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 CCP5OD CCP4OD ECCP3OD U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 140
... PIC18F87J50 FAMILY REGISTER 10-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-1 Unimplemented: Read as ‘0’ bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers 10 ...
Page 141
... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: When PMPMX = 0. 2: Available on 80-pin devices only. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type O DIG LATA< ...
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... PIC18F87J50 FAMILY TABLE 10-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Name Bit 7 Bit 6 PORTA — — LATA — — TRISA — — (1) ANCON0 PCFG7 — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> ...
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... Reading PORTB will end the mismatch condition and allow flag bit, RBIF cleared. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature ...
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... PIC18F87J50 FAMILY TABLE 10-6: PORTB FUNCTIONS TRIS Pin Name Function Setting RB0/FLT0/INT0 RB0 0 1 FLT0 1 INT0 1 RB1/INT1/ RB1 0 PMA4 1 INT1 1 PMA4 x RB2/INT2/ RB2 0 PMA3 1 INT2 1 PMA3 x RB3/INT3/ RB3 0 ECCP2/P2A/ 1 PMA2 INT3 1 (1) ECCP2 0 1 (1) P2A 0 PMA2 x RB4/KBI0/ RB4 0 PMA1 1 KBI0 PMA1 x RB5/KBI1/ ...
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... TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 LATB3 ...
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... PIC18F87J50 FAMILY 10.4 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. Only PORTC pins, RC2 through RC7, are digital only pins and can tolerate input voltages up to 5.5V. PORTC is multiplexed with CCP, MSSP and EUSART peripheral functions (Table 10-8). The pins have Schmitt Trigger input buffers ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY I/O Description Type DIG LATC< ...
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... PIC18F87J50 FAMILY TABLE 10-8: PORTC FUNCTIONS (CONTINUED) TRIS Pin Name Function I/O Setting RC7/RX1/DT1 RC7 RX1 I 1 DT1 Legend Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). ...
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... Port is active, the input buffers are TTL. For more information, refer to Section 11.0 “Parallel Master Port” © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Each of the PORTD pins has a weak internal pull-up. The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. A single control bit can turn off all the pull-ups. This is performed by clearing bit, RDPU (PORTG< ...
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... PIC18F87J50 FAMILY TABLE 10-10: PORTD FUNCTIONS TRIS Pin Name Function Setting RD0/AD0/ RD0 0 PMD0 1 (2) AD0 x x (3) PMD0 x x RD1/AD1/ RD1 0 PMD1 1 (2) AD1 x x (3) PMD1 x x RD2/AD2/ RD2 0 PMD2 1 (2) AD2 x x (3) PMD2 x x RD3/AD3/ RD3 0 PMD3 1 (2) AD3 x x (3) PMD3 ...
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... LATD7 LATD6 TRISD TRISD7 TRISD6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type O DIG LATD<6> data output PORTD<6> data input. O DIG-3 External memory interface, address/data bit 6 output. ...
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... PIC18F87J50 FAMILY 10.6 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. All pins on PORTE are digital only and tolerate voltages up to 5.5V. All pins on PORTE are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: These pins are configured as digital inputs on any device Reset ...
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... External memory interface I/O takes priority over all other digital and PMP I/O. 3: Available on 80-pin devices only. 4: Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 5: Default configuration for PMP (PMPMX Configuration bit = 1). © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type O DIG LATE<0> data output PORTE< ...
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... PIC18F87J50 FAMILY TABLE 10-12: PORTE FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RE5/AD13/ RE5 0 PMA11/P1C 1 (3) AD13 x x PMA11 x (1) P1C 0 RE6/AD14/ RE6 0 PMA10/P1B 1 (3) AD14 x x PMA10 x (1) P1B 0 RE7/AD15/ RE7 0 PMA9/ECCP2/ 1 P2A (3) AD15 x x PMA9 x (4) ECCP2 0 1 (4) P2A 0 Legend Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’ ...
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... To configure PORTF as digital I/O, set the corresponding bits in ANCON0 and ANCON1. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY When Configuration bit, PMPMX = 0, PORTF is multi- plexed with Parallel Master data port. This multiplexing is available only in 80 pin devices. EXAMPLE 10-6: ...
Page 156
... PIC18F87J50 FAMILY TABLE 10-14: PORTF FUNCTIONS TRIS Pin Name Function Setting RF2/PMA5/ RF2 0 AN7/C2INB 1 PMA5 x AN7 1 C2INB x RF3/D- RF3 1 D- RF4/D+ RF4 1 D+ RF5/PMD2/ RF5 0 AN10/C1INB/ CV REF 1 (1) PMD2 x x AN10 1 C1INB REF RF6/PMD1/ RF6 0 AN11/C1INA 1 (1) PMD1 x x AN11 1 C1INA ...
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... PCFG15 PCFG14 PCFG13 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RF5 RF4 ...
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... PIC18F87J50 FAMILY 10.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISG. All pins on PORTG are digital only and tolerate voltages up to 5.5V. PORTG is multiplexed with EUSART2 functions (Table 10-16). PORTG pins have Schmitt Trigger input buffers ...
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... P1D 0 Legend Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY I/O Type O DIG LATG<0> data output. ...
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... PIC18F87J50 FAMILY TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Name Bit 7 Bit 6 PORTG RDPU REPU LATG — — TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’. DS39775B-page 158 ...
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... ANCON1 register. RH3 to RH6 is multiplexed with Parallel Master Port and RH4 to RH6 are multiplexed as comparator pins. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY PORTH can also be configured as the alternate Enhanced PWM output channels B and C for the ECCP1 and ECCP3 modules. This is done by clearing the ECCPMX Configuration bit ...
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... PIC18F87J50 FAMILY TABLE 10-18: PORTH FUNCTIONS TRIS Pin Name Function I/O Setting RH0/A16 RH0 A16 O x RH1/A17 RH1 A17 O x RH2/A18/ RH2 O 0 PMD7 I 1 A18 O x (2) PMD7 RH3/A19/ RH3 O 0 PMD6 I 1 A19 O x (2) PMD6 ...
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... Legend: Shaded cells are not used by PORTH. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY I/O Type DIG LATH<7> data output. ST PORTH<7> data input. ...
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... PIC18F87J50 FAMILY 10.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. All pins on PORTJ are digital only and tolerate voltages up to 5.5V. All pins on PORTJ are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output ...
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... TRISJ TRISJ7 TRISJ6 TRISJ5 PORTG RDPU REPU RJPU Legend: Shaded cells are not used by PORTJ. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output; takes priority over digital I/O ...
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... PIC18F87J50 FAMILY NOTES: DS39775B-page 164 Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 11-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Key features of the PMP module include: • Programmable Address Lines • Two Chip Select Lines • Programmable Strobe Options - Individual Read and Write Strobes or; ...
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... PIC18F87J50 FAMILY 11.1 Module Registers The PMP module has a total of 14 Special Function Registers for its operation, plus one additional register to set configuration options. Of these, 8 registers are used for control and 6 are used for PMP data transfer. 11.1.1 CONTROL REGISTERS The eight PMP Control registers are: • ...
Page 169
... Read strobe active-high (PMRD Read strobe active-low (PMRD) For Master Mode 1 (PMMODEH<1:0> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY (1) (1) (1) R/W-0 R/W-0 CS2P CS1P U = Unimplemented bit, read as ‘ ...
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... PIC18F87J50 FAMILY REGISTER 11-3: PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 BUSY: Busy bit (Master mode only Port is busy 0 = Port is not busy bit 6-5 IRQM1:IRQM0: Interrupt Request Mode bits 11 = Interrupt generated when read buffer 3 is read or write buffer 3 is written (Buffered PSP mode read or write operation when PMA< ...
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... PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O bit 5-0 PTEN13:PTEN8: PMP Address Port Enable bits 1 = PMA<13:8> function as PMP address lines 0 = PMA<13:8> function as port I/O © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘0’ ...
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... PIC18F87J50 FAMILY REGISTER 11-6: PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-2 PTEN7:PTEN2: PMP Address Port Enable bits 1 = PMA<7:2> function as PMP address lines 0 = PMA<7:2> function as port I/O bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA< ...
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... Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY U-0 R-1 R-1 — OB3E OB2E U = Unimplemented bit, read as ‘ ...
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... PIC18F87J50 FAMILY 11.1.2 DATA REGISTERS The PMP module uses 6 registers for transferring data into and out of the microcontroller. They are arranged as three pairs to allow the option of 16-bit data operations: • PMDIN1H and PMDIN1L • PMDIN2H and PMDIN2L • PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L • PMDOUT2H and PMDOUT2L ...
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... Master PMD<7:0> PMCS PMRD PMWR © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is con- figured using the MODE1:MODE0 bits in the PMMODEH register. The setting affects whether the module acts as a slave or a master and it determines the usage of the control pins ...
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... PIC18F87J50 FAMILY 11.2.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD<7:0> is captured into the lower PMDIN1L register. The PMPIF and IBF flag bits are set when the write ends.The timing for the control signals in Write mode is shown in Figure 11-3 ...
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... PMRD PMWR Data Bus Control Lines © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY flow is generated, and the Buffer Overflow flag bit OBUF is set. If all four OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. 11.2.4.2 WRITE TO SLAVE PORT For write operations, the data is be stored sequentially, starting with Buffer 0 (PMDIN1L< ...
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... PIC18F87J50 FAMILY 11.2.5 ADDRESSABLE PARALLEL SLAVE PORT MODE In the Addressable Parallel Slave Port mode ( PMMODEH<1:0> = 01), the module is configured with two extra inputs, PMA<1:0>, which are the address lines 1 and 0. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers ...
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... PMA<1:0> IBF PMPIF © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY output registers and their associated address. When an output buffer is read, the corresponding OBxE bit is set. The OBxE flag bit is set when all the buffers are empty. If any buffer is already empty, OBxE = 1, the next read to that buffer will generate an OBUF event ...
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... PIC18F87J50 FAMILY 11.3 MASTER PORT MODES In its Master modes, the PMP module provides an 8-bit data bus bits of address, and all the necessary control signals to operate a variety of external parallel devices, such as memory devices, peripherals and slave microcontrollers. To use the PMP as a master, ...
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... PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY PMA<13:0> PMD<7:0> PMCS1 PMCS2 Address Bus PMRD Data Bus ...
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... PIC18F87J50 FAMILY 11.3.5 CHIP SELECT FEATURES Up to two chip select lines, PMCS1 and PMCS2, are available for the Master modes of the PMP. The two chip select lines are multiplexed with the Most Signifi- cant bits of the address bus (PMADDRH<6> and PMADDRH<7>). When a pin is configured as a chip select not included in any address auto-increment/ decrement ...
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... PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMA<13:8> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Data Data WAITE<1:0> WAITM< ...
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... PIC18F87J50 FAMILY FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMA<13:8> PMWR PMRD PMALL PMPIF BUSY FIGURE 11-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address< ...
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... WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Data Address<15:8> Data Address< ...
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... PIC18F87J50 FAMILY FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, ...
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... FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY LSB MSB Address<15:8> LSB Q1 ...
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... PIC18F87J50 FAMILY 11.4 Application Examples This section introduces some potential applications for the PMP module. FIGURE 11-27: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION PIC18F PMD<7:0> PMALL PMALH PMCS PMRD PMWR 11.4.2 PARTIALLY MULTIPLEXED MEMORY OR PERIPHERAL Partial multiplexing implies using more pins; however, for a few extra pins, some extra performance can be achieved ...
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... Figure 11-32. In this case the PMP module is config- ured for active-high control signals since common LCD displays require active-high control. FIGURE 11-32: LCD CONTROL EXAMPLE (BYTE MODE OPERATION) PIC18F PM<7:0> PMA0 PMRD/PMWR PMCS © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> D<7:0> A0 ...
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... PIC18F87J50 FAMILY TABLE 11-3: REGISTERS ASSOCIATED WITH PMP MODULE Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL PIR1 PMPIF ADIF PIE1 PMPIE ADIE IPR1 PMPIP ADIP PMCONH PMPEN — PMCONL CSF1 CSF0 (1) PMADDRH / CS2 CS1 (1) PMDOUT1H (1) PMADDRL / (1) PMDOUT1L PMDOUT2H PMDOUT2L PMDIN1H PMDIN1L PMDIN2H PMDIN2L ...
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... Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1. Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
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... PIC18F87J50 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87J50 FAMILY NOTES: DS39775B-page 192 Preliminary © 2007 Microchip Technology Inc. ...
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... Stops Timer1 Note 1: Default (legacy) SFR at this address, available when WDTCON<4> © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F87J50 FAMILY 13.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM Timer1 Oscillator ...
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... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. Type LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F87J50 FAMILY If a high-speed circuit must be located near the oscilla- tor (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 13-4, may be helpful when used on a single-sided PCB or in addition to a ground plane. ...
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... CPFSGT hours RETURN CLRF hours RETURN © 2007 Microchip Technology Inc. PIC18F87J50 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt ; Insert the next 4 lines of code when TMR1 ...
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... PIC18F87J50 FAMILY TABLE 13-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PMPIF ADIF PIE1 PMPIE ADIE IPR1 PMPIP ADIP (1) TMR1L Timer1 Register Low Byte (1) TMR1H Timer1 Register High Byte (1) T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module ...