U62256A Alliance Semiconductor, U62256A Datasheet

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U62256A

Manufacturer Part Number
U62256A
Description
Manufacturer
Alliance Semiconductor
Datasheet

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Features
Pin Configuration
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April 20, 2004
(MIL STD 883C M3015.7)
data outputs
dissipation in long Read Cycles
32768x8 bit static CMOS RAM
Access times 70 ns, 100 ns
Common data inputs and
Three-state outputs
Typ. operating supply current
TTL/CMOS-compatible
Automatical reduction of power
Power supply voltage 5 V + 10 %
Operating temperature ranges
ESD protection > 2000 V
Latch-up immunity >100 mA
Packages: PDIP28 (600 mil)
QS 9000 Quality Standard
DQ0
DQ1
DQ2
VSS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
100 ns: 40 mA
-40 to 85 °C
-40 to 125 °C
70 ns: 50 mA
0 to 70 °C
SOP28 (330 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
PDIP
SOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Description
The U62256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Write
The memory array is based on a
6-transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
The Read cycle is finished by the
- Standby
- Data Retention
1 1
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Pin Description
Address Inputs
Data In/Out
Signal Description
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Standard 32K x 8 SRAM
U62256A

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U62256A Summary of contents

Page 1

... DQ2 16 VSS 14 15 Top View April 20, 2004 Description The U62256A is a static RAM manufactured using a CMOS pro- cess technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the fal- ling edge of E ...

Page 2

... U62256A Block Diagram A10 A11 A12 A13 A14 Address Change Detector Truth Table Operating Mode Standby/not selected Internal Read Read Write * Memory Cell Array 512 Rows Columns Sense Amplifier/ Write Control Logic Clock ...

Page 3

... Symbol stg | Symbol Conditions well as I Min. Max -40 85 -40 125 -65 125 -65 150 200 Min. Max. 4.5 -0.3 2 U62256A Unit °C °C mA Unit 5 0.3 V ...

Page 4

... U62256A Electrical Characteristics Supply Current - Operating Mode Supply Current - Standby Mode (CMOS level) Supply Current - Standby Mode (TTL level) Output High Voltage Output Low Voltage Input High Leakage Current Input Low Leakage Current Output High Current Output Low Current Output Leakage Current ...

Page 5

... CW w( su HZWE dis( HZOE dis( LZWE en( LZOE en( U62256A 10 Unit Max. Min. Max. 100 ns 70 100 ns 70 100 Unit Max. Min. Max. 100 ns 70 ...

Page 6

... U62256A Data Retention Mode 4 Data Retention Characteristics Data Retention Supply Voltage Data Retention Supply Current Data Retention Setup Time Operating Recovery Time Test Configuration for Functional Check measurement dis(E), dis(W) E-Controlled ≥ CC(DR) 2 Data Retention DR - 0.2 V ≤ ...

Page 7

... Leadfree Option blank = Standard Package G1 = Leadfree Green Package Power Consumption blank = Standard (only A-Type Very Low Power Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package U62256A Unit (C/K-Type) ...

Page 8

... U62256A Read Cycle 1: Ai-controlled (during Read Cycle : DQi Output Read Cycle 2: G-, E-controlled (during Read Cycle DQi Output Address Valid t a(A) Previous Data Valid t v( Address Valid t t su(A) a(E) t en(E) t a(G) t en(G) High Output Data Valid t dis(E) ...

Page 9

... The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. April 20, 2004 t cW Address Valid t su(E) t su(A-WH) t w(W) t su(A) t su(D) Input Data Valid t dis(W) High Address Valid t su(A) t w(E) t su(W) t su(D) Input Data Valid t dis(W) High-Z t dis( H-level h(A) t h(D) t en(W) t h( L-level U62256A ...

Page 10

... April 20, 2004 Grenzstraße 28 • D-01109 Dresden • • D-01101 Dresden • Germany Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de Zentrum Mikroelektronik Dresden AG U62256A ...

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