74LVX125MX Fairchild Semiconductor, 74LVX125MX Datasheet

IC BUFFER TRI-ST QD LOW V 14SOIC

74LVX125MX

Manufacturer Part Number
74LVX125MX
Description
IC BUFFER TRI-ST QD LOW V 14SOIC
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Datasheet

Specifications of 74LVX125MX

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
4mA, 4mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Family
LVX
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Maximum Power Dissipation
180 mW
Minimum Operating Temperature
- 40 C
Number Of Lines (input / Output)
4 / 3
Output Type
3-State
Propagation Delay Time
13.6 ns at 2.7 V, 9.7 ns at 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVX125MX
Manufacturer:
MAXIM
Quantity:
500
Part Number:
74LVX125MX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
©1994 Fairchild Semiconductor Corporation
74LVX125 Rev. 1.4.0
74LVX125
Low Voltage Quad Buffer with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
74LVX125M
74LVX125SJ
74LVX125MTC
A
OE
O
n
Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Pin Names
Number
n
All packages are lead free per JEDEC: J-STD-020B standard.
Order
Package
Inputs
Output Enable Inputs
Outputs
Number
MTC14
M14A
M14D
Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
General Description
The LVX125 contains four independent non-inverting
buffers with 3-STATE outputs. The inputs tolerate volt-
ages up to 7V allowing the interface of 5V systems to 3V
systems.
Logic Symbol
Truth Table
H
L
Z
X
Package Description
LOW Voltage Level
High Impedance
Immaterial
HIGH Voltage Level
OE
H
L
L
n
Inputs
A
H
X
IEEE/IEC
L
n
Output
O
H
Z
L
n
February 2008
www.fairchildsemi.com

Related parts for 74LVX125MX

74LVX125MX Summary of contents

Page 1

... Inputs n OE Output Enable Inputs n O Outputs n ©1994 Fairchild Semiconductor Corporation 74LVX125 Rev. 1.4.0 General Description The LVX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate volt- ages allowing the interface of 5V systems to 3V systems. Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5 ...

Page 2

... Input Voltage I V Output Voltage O T Operating Temperature Input Rise and Fall Time Note: 1. Unused inputs must be held HIGH or LOW. They may not float. ©1994 Fairchild Semiconductor Corporation 74LVX125 Rev. 1.4.0 Parameter –0.5V I (1) Parameter 2 Rating –0.5V to +7.0V –20mA –0. –20mA +20mA – ...

Page 3

... Quiet Output Minimum Dynamic V OLV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW Level Dynamic Input Voltage ILD Note: 2. Input t t 3ns r f ©1994 Fairchild Semiconductor Corporation 74LVX125 Rev. 1.4.0 V Conditions Min. Typ. Max. CC 2.0 3.0 3.6 2.0 3.0 3.6 2.0 V ...

Page 4

... Input Capacitance IN C Power Dissipation Capacitance PD Note defined as the value of the internal equivalent capacitance which is calculated from the operating current PD consumption without load. Average operating current can be obtained by the eqation: I ©1994 Fairchild Semiconductor Corporation 74LVX125 Rev. 1.4.0 V (V) Conditions Min. CC 2.7 C 15pF L ...

Page 5

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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