STPCI2 STMicroelectronics, STPCI2 Datasheet - Page 6

• Manufacturer Part Number: STPCI2
• Description: STPC ATLAS DATASHEET - X86 CORE PC COMPATIBLE SYS
• Manufacturer: STMicroelectronics

GENERAL DESCRIPTION
The STPC Atlas implements a multi-function
parallel port. The standard PC/AT compatible
logical address assignments for LPT1, LPT2 and
LPT3 are supported. It can be configured for any
of the following three modes and supports the
IEEE Standard 1284 parallel interface protocol
standards, as follows:
- Compatibility Mode (Forward channel, standard)
- Nibble Mode (Reverse channel, PC compatible)
- Byte Mode (Reverse channel, PS/2 compatible)
The
interface provides a 16-bit I/O facility, using 16
dedicated device pins. It is organised using two
blocks of 8-bit Registers, one for lines 0 to 7, the
other for lines 8 to 15.
Each GPIO port can be configured as an input or
an output simply by programming the associated
port direction control register. All GPIO ports are
configured as inputs at reset, which also latches
the input levels into the Strap Registers. The input
states of the ports are thus recorded automati-
cally at reset, and this can be used as a strap
register anywhere in the system.
1.4. FEATURE MULTIPLEXING
The STPC Atlas BGA package has 516 balls. This
however is not sufficient for all of the integrated
functions available; some features therefore share
the same balls and cannot thus be used at the
same time. The STPC Atlas configuration is done
by ‘strap options’. This is a set of pull-up or pull-
down resistors on the memory data bus, checked
on reset, which auto-configure the STPC Atlas.
There 3 multiplexed functions are the external ISA
bus, the Local Bus and the PCMCIA interface.
1.5. POWER MANAGEMENT
The STPC Atlas core is compliant with the
Advanced
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management
Unit
consumption, providing a comprehensive set of
features that controls the power usage and
supports compliance with the United States
Environmental Protection Agency's Energy Star
Computer Program. The PMU provides the
following hardware structures to assist the
software
consumption:
- System Activity Detection.
- 3 power-down timers detecting system inactivity:
6/111
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
General
(PMU)
in
Power
module
managing
Purpose
Management
Input/Output
controls
the
system
the
Issue 1.0 - July 24, 2002
(GPIO)
(APM)
power
power
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system
performance in various power down states of the
system including full power-on state.
- Power control outputs to disable power from
different planes of the board.
Lack of system activity for progressively longer
periods of time is detected by the three power
down timers. These timers can generate SMI
interrupts to CPU so that the SMM software can
put the system in decreasing states of power
consumption. Alternatively, system activity in a
power down state can generate an SMI interrupt
to allow the software to bring the system back up
to full power-on state. The chip-set supports up to
three power down states described above; these
correspond to decreasing levels of power savings.
Power down puts the STPC Atlas into suspend
mode. The processor completes execution of the
current
instructions and associated bus cycles. During the
suspend mode, internal clocks are stopped.
Removing power-down, the processor resumes
instruction fetching and begins execution in the
instruction stream at the point it had stopped.
Because of the static nature of the core, no
internal data is lost.
1.6. JTAG
JTAG stands for Joint Test Action Group and is
the popular name for IEEE Std. 1149.1, Standard
Test Access Port and Boundary-Scan Architec-
ture. This built-in circuitry is used to assist in the
test, maintenance and support of functional circuit
blocks. The circuitry includes a standard interface
through which instructions and test data are
communicated. A set of test features is defined,
including a boundary-scan register so that a
component is able to respond to a minimum set of
test instructions.
instruction,
any
pending
decoded