MC74HCT125ADG ON Semiconductor, MC74HCT125ADG Datasheet

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MC74HCT125ADG

Manufacturer Part Number
MC74HCT125ADG
Description
IC BUFFER NONINV QUAD 3ST 14SOIC
Manufacturer
ON Semiconductor
Series
74HCTr
Datasheet

Specifications of MC74HCT125ADG

Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
6mA, 6mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Family
74HCT
Number Of Channels Per Chip
4
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Propagation Delay Time
18 ns
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MC74HCT125A
Quad 3-State Noninverting
Buffer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
inputs are compatible with standard CMOS and LSTTL outputs.
with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low.
Features
© Semiconductor Components Industries, LLC, 2009
November, 2009 − Rev. 1
GND
OE1
OE2
The MC74HCT125A is identical in pinout to the LS125. The device
The MC74HCT125A noninverting buffer is designed to be used
PIN ASSIGNMENT
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7A Requirements
Chip Complexity: 72 FETs or 18 Equivalent Gates
These are Pb−Free Devices
A1
Y1
A2
Y2
FUNCTION TABLE
A
H
X
L
Inputs
1
2
3
4
5
6
7
HCT125A
OE
H
L
L
Output
14
13
12
11
10
H
9
8
Y
L
Z
V
OE4
A4
Y4
OE3
A3
Y3
CC
Active−Low Output Enables
OE1
OE2
OE3
OE4
A1
A2
A3
A4
LOGIC DIAGRAM
PIN 14 = V
PIN 7 = GND
10
12
13
2
1
5
4
9
CC
11
3
6
8
1
Y1
Y2
Y3
Y4
14
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
14
14
14
1
1
1
A
L, WL
Y, YY
W, WW
G
G
(Note: Microdot may be in either location)
ORDERING INFORMATION
1
http://onsemi.com
CASE 948G
CASE 751A
SOEIAJ−14
DT SUFFIX
TSSOP−14
CASE 646
CASE 965
N SUFFIX
D SUFFIX
F SUFFIX
SOIC−14
PDIP−14
=
=
=
=
= Pb−Free Package
= Pb−Free Package
Publication Order Number:
14
1
14
Assembly Location
Wafer Lot
Year
Work Week
1
14
MC74HCT125AN
1
14
MC74HCT125A/D
DIAGRAMS
AWLYYWWG
1
74HCT125A
MARKING
HCT125AG
AWLYWW
ALYWG
ALYWG
125A
HCT
G

Related parts for MC74HCT125ADG

MC74HCT125ADG Summary of contents

Page 1

MC74HCT125A Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT125A is identical in pinout to the LS125. The device inputs are compatible with standard CMOS and LSTTL outputs. The MC74HCT125A noninverting buffer is designed to be ...

Page 2

MAXIMUM RATINGS Symbol Parameter V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) out I DC Input Current, per Pin Output Current, per ...

Page 3

... Power Dissipation Capacitance (Per Buffer Used to determine the no−load dynamic power consumption: P ORDERING INFORMATION Device MC74HCT125ANG MC74HCT125ADG MC74HCT125ADR2G MC74HCT125ADTG MC74HCT125ADTR2G MC74HCT125AFG MC74HCT125AFELG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb− ...

Page 4

INPUT 10% t PLH OUTPUT Y 90 10% t TLH V = GND Figure 1. TEST POINT OUTPUT DEVICE UNDER ...

Page 5

−T− SEATING PLANE 0.13 (0.005) PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE http://onsemi.com 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI ...

Page 6

... G −T− SEATING 14 PL PLANE 0.25 (0.010 14X 0.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE 0.25 (0.010 ...

Page 7

... S A −V− C 0.10 (0.004) −T− G SEATING D PLANE 14X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE 0.25 (0.010) ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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