IDT72V2113 Integrated Device Technology, IDT72V2113 Datasheet - Page 4

• Manufacturer Part Number: IDT72V2113
• Description: 256k X 18 / 512k X 9 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

DESCRIPTION (CONTINUED)
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
For applications requiring more data storage capacity than a single FIFO
PAE and PAF can be programmed independently to switch at any point in
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
PROGRAMMABLE ALMOST-FULL (PAF)
FIRST WORD FALL THROUGH/SERIAL
FULL FLAG/INPUT READY (FF/IR)
WRITE CLOCK (WCLK/WR*)
(x9 or x18) DATA IN (D
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
Figure 1. Single Device Configuration Signal Flow Diagram
PARTIAL RESET (PRS)
INPUT (FWFT/SI)
LOAD (LD)
INPUT WIDTH
0
- D
TM
NARROW BUS FIFO
(IW)
n
)
TM
72V2103
72V2113
NARROW BUS FIFO
IDT
4
are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D
of RCLK can be used to read the offsets in parallel from Q
serial or parallel offset loading has been selected.
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-
MASTER RESET (MRS)
OUTPUT WIDTH
For serial programming, SEN together with LD on each rising edge of WCLK,
During Master Reset (MRS) the following events occur: the read and write
The Partial Reset (PRS) also sets the read and write pointers to the first
It is also possible to select the timing mode of the PAE (Programmable Almost-
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
(OW)
RETRANSMIT (RT)
PROGRAMMABLE ALMOST-EMPTY (PAE)
READ CLOCK (RCLK/RD*)
READ ENABLE (REN)
EMPTY FLAG/OUTPUT READY (EF/OR)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
(x9 or x18) DATA OUT (Q
OUTPUT ENABLE (OE)
n
. REN together with LD on each rising edge
COMMERCIAL AND INDUSTRIAL
0
- Q
n
)
TEMPERATURE RANGES
n
regardless of whether
APRIL 6, 2006
6119 drw03