ATA5811 ATMEL Corporation, ATA5811 Datasheet - Page 84

• Manufacturer Part Number: ATA5811
• Description: Ata5811 Uhf Ask/fsk Transceiver
• Manufacturer: ATMEL Corporation

18. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for T
6.6V (2-battery application) and V
otherwise specified.
84
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
13.5
13.6
13.7
14.1
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
No.
14
15
Parameters
Bit-rate range
Minimum time period
between edges at pin
SDO_TMDO in RX
transparent mode
Edge-to-edge time
period of the data signal
for full sensitivity in RX
mode
TX Mode
Start-up time
Configuration of the Transceiver with 4-wire Serial Interface
CS set-up time to rising
edge of SCK
SCK cycle time
SDI_TMDI set-up time
to rising edge of SCK
SDI_TMDI hold time
from rising edge of SCK
SDO_TMDO enable
time from rising edge of
CS
SDO_TMDO output
delay from falling edge
of SCK
SDO_TMDO disable
time from falling edge of
CS
CS disable time period
Time period SCK low to
CS high
ATA5811/ATA5812
VS2
Test Conditions
BR_Range =
BR_Range0
BR_Range1
BR_Range2
BR_Range3
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
From Idle mode
C
L
= 4.75V to 5.25V (car application), typical values at V
= 10 pF
amb
= –40°C to +105°C. V
33, 35
32, 33
32, 33
31, 35
31, 35
31, 33
33, 35
Pin
31
33
35
BR_Range
T
T
T
T
T
T
VS1
T
Symbol
SCK_setup1
Out_disable
Out_enable
T
CS_disable
DATA_min
Out_delay
CS_setup
T
T
T
T
Startup
Cycle
Setup
DATA
Hold
= V
S2
= 2.4V to 3.6V (1-battery application), V
T
10
Min.
XDCLK
200
100
250
250
250
1.0
2.0
4.0
8.0
1.5
T
1.5
T
50
25
2
DCLK
DCLK
VS1
= V
331.5
Typ.
VS2
T
DCLK
= 3V and T
331.5
Max.
10.0
20.0
62.5
500
250
125
250
250
250
T
2.5
5.0
DCLK
amb
= 25°C unless
Kbit/s
Unit
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
ns
4689F–RKE–08/06
VS2
= 4.4V to
Type*
A
A
B
A
A
A
C
C
C
C
C
A
C