CDK1300 Cadeka Microcircuits LLC., CDK1300 Datasheet

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CDK1300

Manufacturer Part Number
CDK1300
Description
8-bit, 250 Msps Adc With Demuxed Outputs
Manufacturer
Cadeka Microcircuits LLC.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CDK1300ITQ44
Manufacturer:
CADEKA
Quantity:
20 000
Company:
Part Number:
CDK1300ITQ44
Quantity:
3 000
Data Sheet
CDK1300
8-bit, 250 MSPS ADC with Demuxed Outputs
Ordering Information
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC
Part Number
CDK1300ITQ44
CDK1300ITQ44_Q
f e a t u r e s
n
n
n
n
n
n
n
n
a p p l i c a t i o n s
n
n
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n
TTL/CMOS/PECL input logic compatible
High conversion rate: 250 MSPS
Single +5V power supply
Very low power dissipation: 310mW
220MHz full power bandwidth
Power-down mode
+3.0V/+5.0V (LVCMOS) digital output
logic compatibility
Single/demuxed output ports selectable
RGB video processing
Digital communications
High-speed instrumentation
Digital Sampling Oscilloscopes (DSO)
Projection display systems
Package
TQFP-44
TQFP-44
Pb-Free
Yes
No
General Description
The CDK1300 is a high-speed, 8-bit analog-to-digital converter implemented
in an advanced BiCMOS process. An advanced folding and interpolating
architecture provides both a high conversion rate and very low power
dissipation of only 310mW. The analog inputs can be operated in
either single-ended or differential input mode. A 2.5V common mode
reference is provided on chip for the single-ended input mode to minimize
external components.
The CDK1300 digital outputs are demuxed (double-wide) with both dual-
channel and single-channel selectable output modes. Demuxed mode
supports either parallel aligned or interleaved data output. The output logic
is both +3.0V and +5.0V compatible. The CDK1300 is available in a 44-lead
TQFP surface mount package over the industrial temperature range of -40°C
to +85°C.
Block Diagram
RoHS Compliant
Yes
No
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
A m p l i fy t h e H u m a n E x p e r i e n c e
Packaging Method
Rail
Rail
www.cadeka.com

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CDK1300 Summary of contents

Page 1

... The CDK1300 digital outputs are demuxed (double-wide) with both dual- channel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0V and +5.0V compatible. The CDK1300 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40°C to +85°C. ...

Page 2

... Data Sheet Pin Configuration TQFP-44 CDK1300 Pin Assignments Pin No. Pin Name Description 40 V Non-inverted analog input; nominally 1V IN Inverted analog input; nominally 1V IN- 16-9 DA –DA Data output bank A; 3V/5V LVCMOS compatible 0 7 19-26 DB –DB Data output bank B; 3V/5V LVCMOS compatible DCLK Non-inverted data output clock; 3V/5V LVCMOS compatible ...

Page 3

Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper ...

Page 4

Data Sheet Electrical Characteristics ( +5V, OV Min A Max CC ƒ = 70MHz, dual channel mode; unless otherwise noted) IN symbol parameter Resolution DC Performance DLE Differential Linearity Error ILE Integral Linearity ...

Page 5

Data Sheet Electrical Characteristics ( +5V, OV Min A Max CC ƒ = 70MHz, dual channel mode; unless otherwise noted) IN symbol parameter Power Supply Requirements AV Analog Voltage Supply ( ...

Page 6

Data Sheet Typical Performance Characteristics ( +5V, OV Min A Max CC ƒ = 70MHz, dual channel mode; unless otherwise noted Performance vs. Temperature 70MHz ...

Page 7

Data Sheet Typical Performance Characteristics ( +5V, OV Min A Max CC ƒ = 70MHz, dual channel mode; unless otherwise noted) IN Input Bandwidth 100 ...

Page 8

... Data Sheet Theory of Operation The CDK1300 is a three-step subranger. It consists of two THAs in series at the input, followed by three ADC blocks. The first block is a three-bit folder with over/under range detection. The second block consists of two single- bit folding interpolator stages. There are pipelining THAs between each ADC block ...

Page 9

Data Sheet ©2008 CADEKA Microcircuits LLC Figure 2. Dual Mode Timing Diagram 9 www.cadeka.com ...

Page 10

... CADEKA Microcircuits LLC CDK1300 Figure 3. Typical Interface Circuit Figure 5. Analog Input Equivalent Circuit Analog Input The input of the CDK1300 can be configured in various ways depending on whether a single-ended or differential input is desired. The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. ...

Page 11

... AGND by external 0.01µF capacitor, as shown in CM Figure 3 on the previous page. Clock Input The clock input on the CDK1300 can be driven by either a single-ended or double-ended clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the clock signal as close to 50% as possible ...

Page 12

... CADEKA or of third parties. Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved. transformer (1:1). An application note (TBD) describing the operation of this board, as well as information on the testing of the CDK1300, is also available. Contact the factory for price and availability of the TBD. INCHES SYMBOL ...

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