WM8734 ETC-unknow, WM8734 Datasheet
WM8734
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WM8734 Summary of contents
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... DESCRIPTION The WM8734 is a low power stereo CODEC ideal for MD, CD-RW machines and DAT recording applications. Stereo line inputs are provided, along with a mute function and programmable line level volume control. Stereo 24-bit multi-bit sigma delta ADCs and DACs are used with oversampling digital interpolation and decimation filters ...
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... MCLK Digital Input 20 DCVDD Supply Note: 1. Pull Up/Down only present when Control Register Interface ACTIVE = 0 to conserve power. w ORDERING INFORMATION - SSOP DEVICE TEMP. RANGE DCVDD XWM8734EDS MCLK SCLK SDIN CSB MODE LLINEIN RLINEIN VMID AGND DESCRIPTION Digital GND Digital Buffers VDD ...
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... Analogue Input 24 LLINEIN Analogue Input 25 MODE Digital Input 26 CSB Digital Input 27 SDIN Digital Input/Output 28 SCLK Digital Input w ORDERING INFORMATION - QFN DEVICE XWM8734EFL ADCLRC 10 ADCDAT 9 DACLRC 8 DACDAT 7 DESCRIPTION Master Clock Input (MCLK) Test Pin, must be left unconnected Digital Core VDD ...
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... WM8734 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process therefore generically susceptible to damage from excessive static voltages ...
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... WM8734 ELECTRICAL CHARACTERISTICS Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER SYMBOL Digital Logic Levels (CMOS Levels) Input LOW level Input HIGH level Output LOW Output HIGH Power On Reset Threshold (DCVDD) DCVDD Threshold On -> Off Hysteresis DCVDD Threshold Off -> On ...
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... WM8734 Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER SYMBOL Line Output for DAC Playback Only (Load = 47k ohms. 50pF) 0dBfs Full scale output voltage SNR (Note 1,2,3) SNR (Note 1,2,3) SNR (Note 1,2,3) Dynamic Range (Note 3) DNR THD Power Supply Rejection Ratio ...
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... SYMBOL System Clock Timing Information T MCLK System clock pulse width high T MCLK System clock pulse width low T MCLK System clock cycle time MCLK Duty cycle DIGITAL AUDIO INTERFACE – MASTER MODE WM8734 CODEC Figure 2 Master Mode Connection w t MCLKL t MCLKH t MCLKY ...
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... BCLK falling edge DACDAT setup time to t DST BCLCK rising edge DACDAT hold time from t DHT BCLK rising edge DIGITAL AUDIO INTERFACE – SLAVE MODE WM8734 CODEC Figure 4 Slave Mode Connection DST DHT o = +25 C, Slave Mode 48kHz, MCLK = 256fs unless ...
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... WM8734 t BCH BCLK DACLRC/ ADCLRC DACDAT ADCDAT Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER SYMBOL Audio Data Input Timing Information BCLK cycle time t BCY BCLK pulse width high t BCH ...
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... WM8734 MPU INTERFACE TIMING CSB SCLK SDIN Figure 6 Program Register Input Timing – 3-Wire MPU Serial Control Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER SYMBOL Program Register Input Information SCLK rising edge to CSB rising t SCS edge ...
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... WM8734 t 3 SDIN t 6 SCLK t 1 Figure 7 Program Register Input Timing – 2-Wire MPU Serial Control Mode Test Conditions AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER SYMBOL Program Register Input Information SCLK Frequency SCLK Low Pulsewidth SCLK High Pulsewidth ...
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... The software control uses either 3-wire MPU interface. AUDIO SIGNAL PATH LINE INPUTS The WM8734 provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external hi-fi or audio equipment. ...
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... WM8734 LINEIN Figure 8 Line Input Schematic The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in 1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD ...
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... C1 forms an RF low pass filter for increasing the rejection of RF interference picked up on any cables. C2 forms a DC blocking capacitor to remove the DC path between the WM8734 and the driving audio equipment. C2 together with the input impedance of the WM8734 form a high pass filter. ...
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... WM8734 The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD ...
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... ADDRESS 0000101 Digital Audio Path Control Table 3 DAC Software Control DAC The WM8734 employs a multi-bit sigma delta oversampling digital to analogue converter. The scheme for the converter is illustrated in Figure 13. FROM DAC DIGITAL FILTERS Figure 13 Multi-Bit Oversampling Sigma Delta Schematic The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality analogue audio ...
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... WM8734 LINE OUTPUTS The WM8734 provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for driving typical line loads of impedance 10K and capacitance 50pF. The line output is used to selectively sum the outputs from the DAC or/and the Line inputs in bypass mode. ...
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... DEVICE OPERATION DEVICE RESETTING The WM8734 contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied ...
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... BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section There are four digital audio interface formats accommodated by the WM8734. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information. ...
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... WM8734 LEFT CHANNEL DACLRC/ ADCLRC BCLK DACDAT ADCDAT MSB Figure 18 Right Justified Mode DSP mode is where the left channel MSB is available on either the 1 (selectable by LRP) following a LRC transition high. Right channel data immediately follows left channel data. 1 BCLK DACLRC/ ADCLRC ...
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... If the ADC is programmed to output bit data then it strips the LSBs from the 24 bit data. If the ADC is programmed to output 32 bits then it packs the LSBs with zeros. If the DAC is programmed to receive bit data, the WM8734 packs the LSBs with zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs. ...
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... Note: If right justified 32 bit mode is selected then the WM8734 defaults to 24 bits. MASTER AND SLAVE MODE OPERATION The WM8734 can be configured as either a master or slave mode device master mode device the WM8734 controls sequencing of the data and clocks on the digital audio interface slave device the WM8734 responds with data to the clocks it receives over the digital audio interface ...
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... DACLRC and the master MCLK. To avoid any timing hazards, refer to the timing section for detailed information. AUDIO DATA SAMPLING RATES The WM8734 provides for two modes of operation (normal and USB) to generate the required DAC and ADC sampling rates. Normal and USB modes are programmed under software control according to the table below. ...
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... The table below should be used to set up the device to work with the various sample rate combinations. For example if the user wishes to use the WM8734 in normal mode with the ADC and DAC sample rates at 48KHz and 48KHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12 ...
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... All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid The BOSR bit represents the base over-sampling rate. This is the rate that the WM8734 digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at 256fs, with BOSR = 1, the base over-sampling rate is at 384fs ...
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... Table 11 Normal Mode Actual Sample Rates 128/192fs NORMAL MODE The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the WM8734 is also capable of being clocked from a 128 or 192fs MCLK for application over limited sampling rates as shown in the table below. SAMPLING ...
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... The table above can be used to set up the device to work with various sample rate combinations. For example if the user wishes to use the WM8734 in USB mode with the ADC and DAC sample rates at 48KHz and 48KHz respectively then the device should be programmed with BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 ...
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... WM8734 the data across the digital interface is correctly synchronised at the 8.021KHz and 44.117KHz rates. The exact sample rates supported for all combinations are defined by the relationships in Table 14 below. TARGET SAMPLING RATE KHz 8 32 44.1 48 88.2 96 Table 14 USB Mode Actual Sample Rates ACTIVATING DSP AND DIGITAL AUDIO INTERFACE To prevent any communication problems from arising across the Digital Audio Interface the Audio Interface is disabled (tristate with weak 100k pulldown) ...
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... If the correct address is received and the R/W bit is ‘0’, indicating a write, then the WM8734 will respond by pulling SDIN low on the next clock pulse (ACK). The WM8734 is a write only device and will only respond to the R/W bit indicating a write. If the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address ...
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... After receiving a complete address and data sequence the WM8734 returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits ...
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... WM8734 0 1 Table 19 Standby Mode In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line inputs, line outputs and headphone outputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode ...
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... WM8734 REGISTER MAP The complete register map is shown in Table 21. The detailed description can be found in the relevant text of the device description. There are 8 registers with 9 bits per register. These can be controlled using either the 2 wire or 3 wire MPU interface. REGISTER ADDRESS 0000000 ...
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... WM8734 REGISTER ADDRESS 0000110 Power Down Control 0000111 Digital Audio Interface Format w BIT LABEL DEFAULT 0 LINEINPD 1 Line Input Power Down 1 = Enable Power Down 0 = Disable Power Down 2 ADCPD 1 ADC Power Down 1 = Enable Power Down 0 = Disable Power Down 3 DACPD 1 DAC Power Down 1 = Enable Power Down ...
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... WM8734 REGISTER ADDRESS 0001000 Sampling Control 0001001 Active Control Table 21 Register Map Description Note: Unused register bits should be set to ‘0’ except when writing to Register 0000110, when bits 1,5 and 6 should be set to ‘1’. DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type and 3 ...
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... WM8734 TERMINOLOGY 1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) 2. Pass-band Ripple – any variation of the frequency response in the pass-band region DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 24 DAC Digital Filter Frequency Response –Type 1 ...
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... Frequency (Fs) Figure 30 ADC Digital Filter Frequency Response –Type 2 ADC HIGH PASS FILTER The WM8734 has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial. H( – – 0.9995 z DIGITAL DE-EMPHASIS CHARACTERISTICS ...
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... WM8734 Figure 34 De-Emphasis Frequency Response (44.1kHz -10 0 5000 10000 15000 Frequency (Fs) Figure 36 De-Emphasis Frequency Response (48kHz) w Figure 35 De-Emphasis Error (44.1kHz) 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 20000 0 5000 Figure 37 De-Emphasis Error (48kHz) Advanced Information 10000 15000 20000 Frequency (Fs) AI Rev 2.2 November 2001 37 ...
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... Interface 10k 15 2-wire Interface MODE 16 CSB 3-wire or 2-wire 17 SDIN MPU Interface 18 SCLK Figure 38 External Components Diagram w 10 AVDD 0 AGND + 8 LOUT 470nF WM8734 Codec + 9 ROUT 470nF 12 VMID 0.1 F MCLK 19 AI Rev 2.2 November 2001 Advanced Information 3. 100 47k 100 47k + ...
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... WM8734 PACKAGE DIMENSIONS (SSOP) DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm Dimensions Symbols (mm) MIN NOM A ----- ----- A 0.05 ----- 1 A 1.65 1. 0.22 ----- c 0.09 ----- D 6.90 7.20 e 0.65 BSC E 7.40 7.80 E 5.00 5. 0.55 0. REF: JEDEC.95, MO-150 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. ...
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... WM8734 PACKAGE DIMENSIONS (QFN) FL: 28 PIN QFN PLASTIC PACKAGE D2 ccc Symbols Dimensions (mm) MIN NOM A 0.90 0.80 0. 0.2 REF 0.18 0.23 b 5.00 BSC D D2 3.2 3.3 5.00 BSC E E2 3.2 3.3 e 0.5 BSC 0.35 0 b(min)/2 Tolerances of Form and Position aaa 0.15 ccc 0.10 REF: JEDEC.95, MO-220, VARIATION VHHD-1 NOTES: 1 ...
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... WM8734 REVISION HISTORY Revision Originator Change Date 2.2 EV 19/11/2001 w History Front Page: Added mention of QFN package; changed SCLK to input only in Block Diagram (was previously drawn as I/O) Page 3: Added QFN pinout diagram, pin description, and order info Pages 2/3, pin descriptions: SDIN changed to I/O (was input ...
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... WM8734 IMPORTANT NOTICE Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability ...