MPC962309-1 Integrated Device Technology, MPC962309-1 Datasheet

MPC962309-1

Manufacturer Part Number

MPC962309-1

Description

Low-cost Lvcmos-input Lvcmos-output 133-mhz 1 9 3.3v Clock Zero Delay Buffer

Manufacturer

Integrated Device Technology

Datasheet

1.MPC962309-1.pdf (17 pages)

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LOW-COST, 3.3V ZERO DELAY BUFFER

IDT™ / ICS™ 3.3V ZERO DELAY BUFFER

clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one

reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin

version of the MPC962309 which drives five outputs with one reference input.

The -1H versions of these devices have higher drive than the -1 devices and can

operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which

lock to an input clock presented on the REF pin. The PLL feedback is on-chip and

is obtained from the CLOCKOUT pad.

Features

•

Functional Description

by the Select Inputs as shown in

outputs are not required. Select inputs also allow the input clock to be directly

applied to the outputs for chip and system testing purposes.

there are no rising edges on the REF input. During this state, all of the outputs

are in tristate, the PLL is turned off, and there is less than 25.0 µA of current draw

for the device. The PLL shuts down in one additional case as shown in

clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less

than 700 ps.

be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.

page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and

MPC962309-1H, are available to provide faster rise and fall times of the base device.

Pentium II is a trademark of Intel Corporation.

The MPC962309 is a zero delay buffer designed to distribute high-speed

The MPC962309 has two banks of four outputs each, which can be controlled

The MPC962305 and MPC962309 PLLs enters a power down state when

Multiple MPC962305 and MPC962309 devices can accept the same input

All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to

The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information

1:5 LVCMOS zero-delay buffer (MPC962305)

1:9 LVCMOS zero-delay buffer (MPC962309)

Zero input-output propagation delay

Multiple low-skew outputs

250 ps max output-output skew

700 ps max device-device skew

Supports a clock I/O frequency range of 10 MHz to 133 MHz,

compatible with CPU and PCI bus frequencies

Low jitter, 200 ps max cycle-cycle, and compatible with Pentium

systems

Test Mode to bypass PLL (MPC962309 only. See

8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin

TSSOP package (MPC962309)

Single 3.3 V supply

Ambient temperature range: –40°C to +85°C

Compatible with the CY2305, CY23S05, CY2309, CY23S09

Spread spectrum compatible

Pb-free packages available

Table

3. Bank B can be tri-stated if all of the

Table

based

Table

MPC962305

MPC962309

MPC962305 REV 7 JULY 16, 2007

8-LEAD TSSOP PACKAGE

16-LEAD SOIC PACKAGE

8-LEAD TSSOP PACKAGE

16-LEAD SOIC PACKAGE

16-LEAD TSSOP PACKAGE

8-LEAD SOIC PACKAGE

Pb-FREE PACKAGE

CASE 751B-05

CASE 948J-01

CASE 751-06

CASE 948F-01

EF SUFFIX

DT SUFFIX

EJ SUFFIX

D SUFFIX

DT SUFFIX

EJ SUFFIX

MPC962305

Related parts for MPC962309-1

MPC962309-1 Summary of contents

Page 1

... The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H, are available to provide faster rise and fall times of the base device. ...

Page 2

... MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER Block Diagram PLL REF S2 Select Input Decoding S1 Table 1. Pin Description for MPC962309 Pin Signal (1) 1 REF (2) 2 CLKA1 (2) 3 CLKA2 GND (2) 6 CLKB1 (2) 7 CLKB2 ( ( (2) 10 CLKB3 (2) 11 CLKB4 12 GND ...

Page 3

... Operating Temperature (Ambient Temperature Load Capacitance, below 100 MHz L C Load Capacitance, from 100 MHz to 133 MHz L C Input Capacitance IN Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices Parameter Description V Input LOW Voltage IL V Input HIGH Voltage IH I Input LOW Current ...

Page 4

... Cycle to Cycle Jitter J t (2) PLL Lock Time LOCK 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices Parameter Name t Output Frequency 1 ( ÷ t1 Duty Cycle ( ÷ ...

Page 5

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER t 5 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 1. Output-to-Output Skew ...

Page 6

... MPC962305EF-1HR2 MPC962305DT-1H MPC962305DT-1HR2 MPC962305EJ-1H MPC962305EJ-1HR2 MPC962309D-1 MPC962309D-1R2 MPC962309EF-1 MPC962309EF-1R2 MPC962309D-1H MPC962309D-1HR2 MPC962309EF-1H MPC962309EF-1HR2 MPC962309DT-1H MPC962309DT-1HR2 MPC962309EJ-1H MPC962309EJ-1HR2 IDT™ / ICS™ 3.3V ZERO DELAY BUFFER 0.1 µF CLK OUT C LOAD 0.1 µF Test Circuit for t 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel ...

Page 7

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 751-07 ISSUE U 8-LEAD SOIC PLASTIC PACKAGE 7 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 8

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 751-07 ISSUE U 8-LEAD SOIC PLASTIC PACKAGE 8 PAGE PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 9

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 751B-05 ISSUE L 16-LEAD SOIC PLASTIC PACKAGE 9 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 10

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 751B-05 ISSUE L 16-LEAD SOIC PLASTIC PACKAGE 10 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 11

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 948F-01 ISSUE B 16-LEAD TSSOP PLASTIC PACKAGE 11 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 12

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 948F-01 ISSUE B 16-LEAD TSSOP PLASTIC PACKAGE 12 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 13

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 948F-01 ISSUE B 16-LEAD TSSOP PLASTIC PACKAGE 13 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 14

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 948J-01 ISSUE B 8-LEAD TSSOP PLASTIC PACKAGE 14 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 15

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 948J-01 ISSUE B 8-LEAD TSSOP PLASTIC PACKAGE 15 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 16

MPC962305 LOW-COST, 3.3V ZERO DELAY BUFFER IDT™ / ICS™ 3.3V ZERO DELAY BUFFER PACKAGE DIMENSIONS CASE 948J-01 ISSUE B 8-LEAD TSSOP PLASTIC PACKAGE 16 PAGE MPC962305 REV 7 JULY 16, 2007 ...

Page 17

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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