AL4CE205 AverLogic Technologies Inc, AL4CE205 Datasheet - Page 2

• Manufacturer Part Number: AL4CE205
• Description: 256, 512, 1k, 2k, 4k X 18 Advanced Synchronous Fifos
• Manufacturer: AverLogic Technologies Inc

independently at a maximum speed of 133 MHz.
The built-in address decoder and pointer managing
circuits provide a straightforward bus interface to
serially read/write memory that reduces inter-chip
design efforts. The AL4CE2x5 embedded memory
array and high performance process technologies
with extended controller functions (read skip, fixed
and programmable status flags.. etc.) offer flexible
memory management.
These FIFOs support up to 18bit input and output
data bus-width that is controlled by separate clock
and enable signals respectively. The input data is
acquired at each rising edge of a free running write
clock while a write enable control pin is asserted.
The output data is available after each rising edge
of a free running read clock while a read enable
and output enable control pins are asserted. When
output enable (/OE) is LOW, the data output bus
is active. If /OE is HIGH, the output data bus will
be in a high-impedance. This signal can control
whether the data is going to be skipped during the
read operation.
The
programmable Almost Full/Almost Empty flags
are powerful functions that can help controlling
A
The 18bit input and output ports operate
VER
L
/WEN
OGIC
WCLK
FIFO
Input data bus
/LD
/RS
T
ECHNOLOGIES
Full/Empty,
Regissers
Write Control
Offset
Write Pointer
Reset Logic
Logic
, I
Buffer
Figure 1. AL4CE2x5 FIFO Block Diagram
Input
NC
.
TEL
Half-Full
: 1 408 361-0400
x18 Memory
1k ,2k, 4k)
(256,512,
and
Array
e-mail: [e-mail]
software to manipulate the FIFO more easily or to
do retransmit operation.
Bus-Matching feature can flexibly configure input
and output bus width. The chip can automatically
convert the input data bus width to match up
output data bus width by packing or unpacking the
data. A Big-Endian/Little-Endian data word
format is provided to invert the read-in bytes
sequence for output. And the Retransmit function
allows data to be reread from the FIFO more than
once.
These chips are available as a 64pin TQFP and
STQFP Package
D
ISTRIBUTED BY
Control Logic
Read Control
Flag Logic
Read Pointer
Output
Buffer
Logic
:
Output data bus
/OE
URL: www.averlogic.com
RCLK
/REN
/OW
/BEB
/FF
/PAE
/EF
/HF
/PAF
/IW
/RT
July 10, 2001