MC74HC244AFELG ON Semiconductor, MC74HC244AFELG Datasheet - Page 5

• Manufacturer Part Number: MC74HC244AFELG
• Description: IC BUFF/DVR TRI-ST DUAL 20SOEIAJ
• Manufacturer: ON Semiconductor
• Series: 74HCr

Specifications of MC74HC244AFELG

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 4
• Current - Output High, Low: 7.8mA, 7.8mA
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (5.3mm Width), 20-SO, 20-SOEIAJ
• Logic Family: HC
• Number Of Channels Per Chip: 8
• Polarity: Non-Inverting
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 7.8 mA
• Low Level Output Current: 7.8 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 55 C
• Number Of Lines (input / Output): 8 / 3
• Output Type: 3-State
• Propagation Delay Time: 96 ns at 2 V, 50 ns at 3 V, 18 ns at 4.5 V, 15 ns at 6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INPUTS
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17)
form on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
Enable A, Enable B (Pins 1, 19)
to these pins, the outputs are enabled and the devices
DATA INPUT
Data input pins. Data on these pins appear in noninverted
Output enables (active−low). When a low level is applied
YA OR YB
OUTPUT
A OR B
*Includes all probe and jig capacitance
t
DEVICE
UNDER
PLH
t
TEST
r
Figure 3. Test Circuit
t
TLH
10%
10%
50%
50%
90%
90%
OUTPUT
Figure 1.
TEST POINT
C
L
*
t
f
t
PHL
SWITCHING WAVEFORMS
t
THL
V
GND
PIN DESCRIPTIONS
CC
http://onsemi.com
TEST CIRCUITS
5
OUTPUT Y
OUTPUT Y
DEVICE
UNDER
function as noninverting buffers. When a high level is
applied, the outputs assume the high impedance state.
OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
output−enable pins, these outputs are either noninverting
outputs or high−impedance outputs.
TEST
ENABLE
A OR B
Device outputs. Depending upon the state of the
*Includes all probe and jig capacitance
OUTPUT
50%
Figure 4. Test Circuit
TEST POINT
50%
50%
t
t
PZL
PZH
C
Figure 2.
1 kW
L
*
t
t
PHZ
PLZ
CONNECT TO V
TESTING t
CONNECT TO GND WHEN
TESTING t
10%
90%
PLZ
PHZ
AND t
AND t
CC
V
GND
HIGH
IMPEDANCE
V
V
HIGH
IMPEDANCE
CC
OL
OH
WHEN
PZL
PZH
.
.