EVX10AS008BGL ETC-unknow, EVX10AS008BGL Datasheet
EVX10AS008BGL
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EVX10AS008BGL Summary of contents
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Datasheet - Preliminary Specification Features • 10-bit Resolution ADC • 2.2 Gsps Sampling Rate • Ascending Compatibility with e2v AT84AS008 10-bit 2.2 Gsps ADC • 500 mVpp Full-scale Analog Input Range • 100Ω Differential or 50Ω Single-ended Analog input and ...
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Applications – Broadband Direct RF Down Conversion – Wide Band Satellite Receivers – Phased Array Antennas, Radars and ECM – High-speed Instrumentation and High-speed Acquisition Systems – High Energy Physics – Automatic Test Equipment 1. Description The EV10AS008B 10-bit 2.2 ...
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Ascending Compatibility with AT84AS008 The EV10AS008B is fully compatible to the AT84AS008 in terms of pinout and functionality. The EV10AS008B is supplied with +3.3V, –2.2V, +2.5V instead of + 5V, –5V, +1.45V. The digital control inputs (DRRB, PGEB, SDA, ...
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Functional Description The EV10AS008B is a 10-bit 2.2 Gsps ADC. The device includes a front-end Track and Hold stage (T/H), followed by an analog encoding stage (Analog Quantizer) which outputs analog residues resulting from analog quantization. Successive banks of ...
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Recommended Conditions of Use Table 3-2. Recommended Conditions of Use Parameter Symbol Positive supply voltage V CC Positive digital supply V (Note:) PLUSD voltage Negative supply voltages V EE Differential analog input INB voltage (full-scale) ...
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Electrical Characteristics • 3.3V • 500 mVpp (full-scale differential Input). Clock inputs differential driven; analog-input IN INB differential driven Table 3-3. Electrical Operating Characteristics Parameter Resolution Power Requirements Power supply voltage ...
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Table 3-3. Electrical Operating Characteristics (Continued) Parameter Clock inputs Clock inputs common voltage range (V (DC coupled clock input) AC coupled for LVDS compatibility Clock input power level (low-phase noise sinewave input) 100Ω differential Clock input power level (low-phase noise ...
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Table 3-3. Electrical Operating Characteristics (Continued) Parameter DC Accuracy DNLrms (1) Differential nonlinearity (1) Differential nonlinearity (1) Integral nonlinearity (1) Integral nonlinearity (2) Gain central value Gain error drift Input offset voltage Notes: 1. Histogram testing 390 ...
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Table 3-4. AC Electrical Characteristics (Continued) Parameter Total Harmonic Distortion (nine harmonics 1.4 Gsps Fin = 700 MHz Fs = 1.7 Gsps Fin = 1.7 GHz Fs = 2.2 Gsps Fin = 1.1 GHz Fs = 2.2 Gsps ...
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Table 3-5. Transient and Switching Performances (Continued) Parameter Output rise/fall time for data ready (3) (20% to 80%) (4) Data output delay (4) Data ready output delay Output Data to Data Ready propagation delay Data ready to output data propagation ...
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Functions Description Table 3-7. Functions Description Name Function V Positive power supply:+ 3. Positive power supply for LVDS buffers: + 2.5V PLUSD V Negative power supply: –2.2V (substrate) EE VIN,VINB Differential analog input CLK,CLKB Differential clock input ...
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Timing Diagram Figure 3-1. Timing Diagram N Analog input External clock Internal clock Latch 1 Latch 2 Regeneration Latch 3 Latches Latch 4 Latch 5 Logic Decoding Latches Latch 6 Latch 7 Latch 8 Output Latches Latch 9 Data ...
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Coding Table 3-8. ADC Coding Table Differential Analog Input Voltage Level > +250.25 mV >Top end of full-scale + ½ LSB +250.25 mV Top end of full-scale + ½ LSB +249.75 mV Top end of full-scale – ½ LSB ...
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Pin Description Table 4-1. Pin Description (CBGA 152 and CI-CGA152) Symbol Pin Number Power Supplies V K1, K2, J3, K3, B6, C6, A7, B7, C7, P8, Q8 B1, C1, D1, G1, M1, Q1, B2, C2, D2, E2, ...
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Table 4-1. Pin Description (CBGA 152 and CI-CGA152) (Continued) Symbol Pin Number PGEB A9 DRRB SDA A6 SDAEN P1 e2v semiconductors SAS 2008 EV10AS008B Function Active high pattern generator enable - digitized input delivered at outputs according ...
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Figure 4-1. CBGA152 and CI-CGA152 Pinout Notes required balls can be electrically connected to GND if simplifying PCB routing. 2. The pinout is given with a bottom view. The way the columns and rows were defined ...
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Package Description 4.1.1 Hermetic CBGA 152 Outline Dimensions Ceramic body size: 21 × Ball pitch: 1.27 mm Cofired: Al2O3 Optional: discrete capacitor mounting lands on top side of package for extra decoupling. Figure 4-2. Mechanical Description Bottom ...
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Cross Section Cross Section 18 0811A–BDC–12/08 CBGA 152 21x21 mm Cross Section 10 bits/2.2 Gsps ADC. External heatsink required Al2O3 ceramic CuW heatspreader brazed on Al2O3 at VEE=-5 Volt potential Location for external heatsink 1.25 +/- 0.12 mm 0.65 ...
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Mechanical Up View Figure 4-3. Isometric View Figure 4-4. Package Top View 4.335 mm 2.50 mm CuW 7 brazed on 9 metallization e2v semiconductors SAS 2008 21. 7. 9.00 mm ...
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Figure 4-5. Package Top View with Optional Discrete Capacitors 2.50 mm CuW 7 brazed on 9 metalization Note: For additional decoupling of the power supplies, extra land capacitors have been foreseen as shown in this ...
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CI-CGA Mechanical Description Figure 4-6. CI-CGA 152 Mechanical Description (Bottom View) Package Chamfer 0.4 (x4) SCI Chamfer 1.8 (x4) 16 Pb90Sn10 columns Pin A1 Index (no column) e2v semiconductors SAS 2008 A 21.00 mm +/- 0.20 152 x O ...
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Figure 4-7. Hermetic CI-CGA 152 Cross Section CuW heat spreader AI203 plate brazed on CuW All units 0811A–BDC–12/08 This side has no metalization (0.300) (0.150) (0.500) 1.62 +/- 0.075 (0.30 +/- 0.05) 0.80 +/- 0.09 1.55 +/- ...
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Figure 4-8. CI-CGA 152 Package Top View R 7. 6.70 mm Nickel gold finishing that defines the external heat sink footprint location (electrically isolated from CuW) Top surface is AI203 ceramic CuW vertical side is apparent at peripheral ...
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Thermal and Moisture Characteristics 5.1 Dissipation by Conduction and Convection (CBGA 152) The thermal resistance from junction to ambient RTH mandatory to use an external heatsink to improve dissipation by convection and conduction. The heat- sink should be fixed ...
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Cooling system efficiency can be monitored using the temperature sensing diodes, integrated in the device. 5.2 Thermal Dissipation by Conduction Only (CBGA 152) When external heatsink cannot be used the relevant thermal resistance is thermal resistance from junc- tion to ...
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Figure 5-2. Black Anodized Aluminium Heat Sink Glued on a Copper Base Screwed on Board (all dimensions in mm) 2 0.3 6.5 Note: The cooling system efficiency can be monitored using the temperature sensing diodes, integrated in the device 5.3.1 ...
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Figure 5-3. Thermal Net Silicon Junction Silicon Die 14.4 mm2 = 0.95 W/cm/˚C Epoxy/Ag glue = 0.02 W/cm/˚C CuW heatspreader = 2.3 W/cm/˚C CuW heatspreader = 2.3 W/cm/˚C Ceramic package = 0.17 W/cm/˚C 0.56 Ceramic ˚C/Watt 2.05 columns PbSn ˚C/Watt ...
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Figure 6-2. Clock Input Equivalent Schematics and ESD Protection CLK 50Ω controlled impedance line (Package) Package PACKAGE GND Pins CLKB Note: 100Ω termination mid point is on chip and AC coupled to ground through capacitor. Figure 6-3. ...
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Figure 6-4. GA and SDA: Gain Adjust and Sampling Delay Adjust, Equivalent Input Schematics ESD GA SDA ESD Figure 6-5. Digital Control Inputs (B/GB, PGEB, SDAEN) Equivalent Inputs Schematics and ESD Protection +1.4V Common mode Vohmin : +1.7V Volmax : ...
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Figure 6-6. Data Ready (DRRB) Equivalent Input Schematic and ESD Protection Vohmin: +1.5V 1.15V common mode 0.4V minimum swing DRRB 30 0811A–BDC–12/08 ESD 16K 5K Volmax : +0.8V Ref ESD VEE = - 2.2V ( Sub) EV10AS008B VCC = +3.3V ...
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Definition of Terms Table 7-1. Definition of Terms Term Maximum sampling Fs max frequency Minimum sampling Fs min frequency BER Bit error rate FPBW Full power input bandwidth SSBW Small signal input bandwidth Signal-to-noise and SINAD distortion ratio SNR ...
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Table 7-1. Definition of Terms (Continued) Term JITTER Aperture uncertainty TS Settling time ORT Overvoltage recovery time TOD Digital data output delay TDR Data ready output delay Time delay from data TD1 transition to data ready Time delay from data ...
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EV10AS008B Application Information 8.1 Timing Information 8.1.1 Timing Value for EV10AS008B Timing values are defined in account package transmission line, bond wire, pad and ESD protections capacitance, and specified ter- mination loads. Evaluation board propagation delays in 50Ω controlled ...
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ADCs or using a single ADC with demultiplexed outputs. Without data ready signal initializa- tion impossible to store the output digital data in a defined order. When used with e2v AT84CS001 1:2/1:4 10 bit DMUX ...
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Timing Diagram with Data Ready Reset Figure 8-1. EV10AS008B Timing Diagram (2 Gsps Clock Rate) Data Ready Reset, Clock Held at Low Level INB CLK/CLKB TOD = 360 ps Digital Outputs TDR = 360 ps Data ...
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Analog Inputs (VIN/VINB) 8.3.1 Static Issues: Differential vs. Single-ended (Full-scale Inputs) The ADC front-end Track and Hold differential preamplifier has been designed in order to be entered either in differential mode or single-ended mode maximum operating speed ...
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Clock Inputs (CLK/CLKB) The EV10AS008B clock inputs are designed for either single-ended or differential operation. The EV10AS008B clock inputs are on- chip 100Ω coupled to ground through chip capacitor. Therefore either ground or different ...
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Equivalent Single-ended Clock Inputs Voltage Levels (1 dBm Single ended on 50Ω Recommended) Figure 8-6. Single-ended Clock Input (Ground Common Mode) 8.5 Noise Immunity Information Circuit noise immunity performance begins at design level. Efforts have been made on the ...
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LVDS Differential Output Loading Configurations Figure 8-7. 50Ω Terminated Differential Outputs VPLUSD = +2.5V 8.6.2 LVDS Logic Compatibility Figure 8-8. LVDS Format (cf. IEEE Std 1596.3- 1994): (1125 mV < common mode < 1375 mV) and 250 mV < ...
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ADC Main Functions 8.7.1 Out-of-range Bit (OR/ORB) It goes to logical high state when the input exceeds the positive full-scale or falls below the negative full- scale. When the analog input exceeds the positive full-scale, the digital outputs remain ...
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Figure 8-9. Diode Pin implementation of Die Junction Temperature Monitoring Function Only Figure 8-10. Junction Temperature Diode Transfer Function The forward voltage drop, (VDIODE) across diode component, vs. junction temperature, (including chip parasitic resistance), is given below (IDIODE = 1 ...
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ADC Gain Control The ADC gain is adjustable by the means of the pin R9 of CBGA package. Figure 8-11. Gain Adjust Transfer Function 8.7.7 Sampling Delay Adjust Sampling delay adjust (SDA pin) allows to fine tune the sampling ...
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... Ordering Information Part Number Package EVX10AS008BGL CBGA152 EV10AS008BCGL CBGA152 EV10AS008BVGL CBGA152 EV10AS008BMGS CI-CGA152 EVX10AS008BGLY CBGA152 RoHS EV10AS008BCGLY CBGA152 RoHS EV10AS008BVGLY CBGA152 RoHS EV10AS008BGL-EB CBGA152 e2v semiconductors SAS 2008 Temperature Range Screening Level Ambient Prototype Commercial C grade Standard 0°C < < 90°C ...
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Appendices Datasheet Status This datasheet contains target and goal specifications for discussion Objective specification with the client and application validation This datasheet contains target and goal specifications for product Target specification development Preliminary specification This datasheet contains preliminary data. ...
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Table of Contents 1 Description ............................................................................................... 2 1.1 2 Functional Description ............................................................................ 4 3 Specifications ........................................................................................... 4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4 Pin Description ....................................................................................... 14 4.1 5 Thermal and Moisture Characteristics ................................................. 24 5.1 5.2 5.3 ...
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