ZY1207 Power-One, ZY1207 Datasheet - Page 13

• Manufacturer Part Number: ZY1207
• Description: 3v To 14v Input 0.5v To 5.5v Output
• Manufacturer: Power-One

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7.
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up
REV. 1.3 MAR 27, 2006
PGOOD
DELAY
TEMP
VOUT
PGND
Name
VLDO
CCA0
CCA1
CCA2
INTL2
INTL3
INTL4
SYNC
VREF
TRIM
ENP
+VS
VIN
Pin
CS
OK
EN
IM
Pin Assignments and Description
Pin
No.
19-
25-
32-
10
11
12
13
14
15
16
17
18
23
24
31
36
1
2
3
4
5
6
7
8
9
Type
Pin
I/O
I/O
I/O
I/O
P
A
A
A
A
P
P
P
I
I
I
I
I
I
I
I
I
I
Buffer
Type
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Compensation Coefficient Address
Compensation Coefficient Address
Compensation Coefficient Address
Frequency Synchronization Line
Temperature Measurement
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Positive Voltage Sense
Enable Logic Selection
Low Voltage Dropout
Current Share/Sense
Output Voltage Trim
Voltage Reference
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Pin Description
Power-Up Delay
Interleave Mode
Interleave Bit 2
Interleave Bit 3
Interleave Bit 4
Output Voltage
Power Ground
Input Voltage
Power Good
Fault Status
Enable
Bit 0
Bit 1
Bit 2
3V to 14V Input
ZY1207 7A No-Bus POL Data Sheet
PGND to program the Power-Up delay. Leave
Connect to CS pin of other Z-POLs connected
Connect to the positive point close to the load
Tie to PGND for Negative logic or leave open
Connect to SYNC pin of other Z-POLs and/or
Connect to an external voltage source higher
Tie to PGND for master or leave open to set
than 4.75V, if V
To program the output voltage, connect a
Connect to OK pin of other Z-1000 POLs.
To program the output voltage, connect a
Connect a capacitor between the pin and
Analog voltage proportional to junction
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
resistor between VREF and TRIM
resistor between VREF and TRIM
Polarity is determined by ENP pin
interleave by INTL0…INTL4 pins
to an external clock generator
temperature of the controller
Leave open, if not used
x
open for zero delay
for Positive logic
0.5V to 5.5V Output
IN
V
in parallel
<4.75V. Connect to V
IN
Notes
_4.75V
Page 13 of 18
IN
, if