ZY1115 Power-One, ZY1115 Datasheet - Page 13

• Manufacturer Part Number: ZY1115
• Description: Zy1115 15a No-bus Pol
• Manufacturer: Power-One

7.
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up
ZD-00696 REV. 1.4
PGOOD
DELAY
PGND
Name
VLDO
TEMP
SYNC
INTL4
INTL3
INTL2
INTL1
INTL0
VOUT
CCA2
CCA1
CCA0
VREF
TRIM
ENP
+VS
-VS
VIN
Pin
OK
EN
CS
IM
Pin Assignments and Description
Pin
No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Type
Pin
I/O
I/O
I/O
I/O
P
A
A
A
A
P
P
P
I
I
I
I
I
I
I
I
I
I
I
I
I
Buffer
Type
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
Compensation Coefficient Address
Compensation Coefficient Address
Compensation Coefficient Address
Frequency Synchronization Line
Temperature Measurement
Negative Voltage Sense
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Positive Voltage Sense
Enable Logic Selection
Low Voltage Dropout
Current Share/Sense
Output Voltage Trim
Voltage Reference
Pin Description
Interleave Mode
Power-Up Delay
Interleave Bit 4
Interleave Bit 3
Interleave Bit 2
Interleave Bit 1
Interleave Bit 0
Output Voltage
Power Ground
Input Voltage
Power Good
Fault Status
Enable
Bit 2
Bit 1
Bit 0
3V to 14V Input
ZY1115 15A No-Bus POL Data Sheet
PGND to program the Power-Up delay. Leave
Connect to the negative point close to the load
Connect to CS pin of other Z-POLs connected
Connect to the positive point close to the load
Tie to PGND for Negative logic or leave open
Connect to SYNC pin of other Z-POLs and/or
Connect to an external voltage source higher
Tie to PGND for master or leave open to set
than 4.75V, if V
Connect to OK pin of other Z-1000 POLs.
Connect a capacitor between the pin and
To program the output voltage, connect a
To program the output voltage, connect a
Analog voltage proportional to junction
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
Tie to PGND for 0 or leave open for 1
resistor between VREF and TRIM
resistor between VREF and TRIM
Polarity is determined by ENP pin
interleave by INTL0…INTL4 pins
to an external clock generator
temperature of the controller
Leave open, if not used
•
open for zero delay
for Positive logic
0.5V to 5.5V Output
IN
V
in parallel
<4.75V. Connect to V
IN
Notes
≥4.75V
Page 13 of 17
IN
, if