SKY73103-11 Skyworks Solutions, Inc., SKY73103-11 Datasheet - Page 8

• Manufacturer Part Number: SKY73103-11
• Description: Sky73103-11 1460-1665 Mhz High Performance Vco/synthesizer With Integrated Switch
• Manufacturer: Skyworks Solutions, Inc.

DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Table 8. DPLL Signal Mapping
VCO Prescalers
The VCO prescalers divide the VCO output signal by either 16/17
or 8/9. The
17 in the 16/17 mode, or whether to divide by 8 or 9 in the 8/9
mode. The prescaler mode is determined by bit [23] of Word 0
(Operation Mode Register).
N-Counter
The N-counter consists of two asynchronous ripple counters, a 6-
bit M-counter and a 4-bit A-counter. The M-counter determines
the counts using the lower division ratio in the prescaler (8 or 16);
the A-counter determines the counts using the upper division ratio
(9 or 17).
By changing the counter setting at each reference clock cycle, the
Modulated Fractional Divider (MFD) achieves the desired noise
shaping.
VCO MFD Block
The MFD block divides down the prescaler output to the internal
PLL comparison frequency. A third order cascaded
technique minimizes spurs through randomization of the division
ratio.
8
modulator determines whether to divide by 16 or
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
November 30, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200649D
dpll_temp_comp_en
dpll_temp_comp(0)
dpll_temp_comp(1)
dpll_temp_comp(2)
dpll_temp_comp(3)
dpll_temp_comp(4)
dpll_flag_override
Serial Port Name
dpll_ext_test(0)
dpll_ext_test(1)
dpll_ext_test(2)
dpll_ext_test(3)
dpll_ext_test(4)
dpll_ext_test(5)
dpll_ext_test(6)
dpll_ext_test(7)
dpll_flag_value
dpll_clk_dly(0)
dpll_clk_dly(1)
modulation
Load Register Word 1 Bit
10
11
12
13
14
15
16
17
18
19
2
3
4
5
6
7
8
9
The MFD block controls the division ratio by dynamically
programming the M and A counters.
Phase Detector and Charge Pump
The phase detector and charge pump detect and integrate the
phase and frequency errors of the divided-down VCO output
versus the reference clock. This results in a feedback adjustment
of the control voltage for the VCO.
Lock Detect
Lock detection circuitry provides a CMOS logic level indication
when the PLL is frequency locked (high when locked).
Reference Input Divider
The R-counter (reference input clock divider) consists of three
divide-by-two blocks and one multiplexer controlled by the rdiv
parameter in Word 2 (Frequency Control 1 Register). The R-
counter is used to select a divide-by-one or a divide-by-eight
function.
Recommended Operation Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0