BU8272GUW ROHM Co. Ltd., BU8272GUW Datasheet
BU8272GUW
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BU8272GUW Summary of contents
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... GPIO ICs Series GPIO Expander IC BU8272GUW ●Description GPIO expander is useful especially for the application that is in short of IO ports. It can 1. Control GPIO output states Know GPIO input states by I Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander. ...
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... BU8272GUW ● Package Specification（VBGA035W040） www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Fig.1 Package Specification 2/17 Technical Note 2009.09 - Rev.A ...
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... BU8272GUW ● Pin Diagram F VDD GPIO0 INT GND E XRST SCL D C ADR SDA GPIO19 B A VDDI2C GPIO18 1 www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. GPIO1 GPIO3 GPIO2 GPIO4 GND GND GND GND GPIO17 GPIO15 GPIO16 GPIO14 Fig.2 Pin Diagram（Bottom View） ...
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... BU8272GUW ● Block Diagram INT VDDI2C ADR SCL Input Filter SDA Reset XRST VDD www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Functional Block Diagram Interrupt INT_MASK Logic IN/OUT Control Bus Shift Control Register Write Pulse Read Pulse Fig.3 Functional Block Diagram ...
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... BU8272GUW ● Electrical Specification VDD=1.8V, VDDIO=3.0V, VDDI2C=3.0V, Ta=25 Item Symbol Input H Voltage Input L Voltage Input H Current Input L Current Output H Voltage Output L Voltage SCL clk frequency Bus free time （repeat）Start condition tSU:STA Setup Time （repeat）Start condition tHD:STA Hold Time SCL Low Time ...
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... BU8272GUW ● Pin-out Functional Descriptions 1. Pin table PIN Land PIN name I/O No. number 1 A1 VDDI2C 2 (NC GND 4 C1 ADR SDA INOUT 6 D1 SCL XRST INT OUT 9 E2 GND 10 F1 VDD 11 F2 GPIO0 INOUT 12 D3 GND 13 F3 GPIO1 INOUT ...
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... BU8272GUW 2. Equivalent IO circuit diagram A www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. B Fig.4 Equivalent IO circuit diagram 7/17 Technical Note C 2009.09 - Rev.A ...
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... Please pull-up SDA and SCL to the same potential of voltage as BU8272GUW is controlled by using an on-chip 2-Wire slave interface. Two kinds of the device address, “0001111” at ADR=”1” or “0001000” at ADR=”0” can be used. The transfer bit rate supports Fast-mode up to max 400Kbps. ...
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... SCL START condition 1.5 Writing protocol A writing protocol is shown in Fig.8-5 below. GPIO register address in BU8272GUW is transferred after one byte of slave address with a write commend. The 3 byte transfer, the register address will be automatically increased. However, when the register address increased to the final address (09h), it will be reset to (00h) after the byte transfer. ...
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... BU8272GUW 1.6 Reading protocol After Writing the slave address and Read/Write commend bits, the next byte is read. The reading register address is next of previous accessed address. Therefore, the data is read with address increment. When the address in increased to the last, the following read address will be reset to (00h). When the GPIO port [19:16] is read, 4 bits of “0” will be added from MSB, and the value of 4 bits from GPIO port [19:16] is read from 2-wire interface ...
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... BU8272GUW 1.8 Timing Diagram Transfer (Repeat) Start state condition t SU;STA SCL SDA t t BUF HD;STA www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. BIT 7 BIT 6 Ack t t 1/f LOW HIGH SCLK t t SU;DAT HD;DAT Fig. 12 Timing Diagram 11/17 Technical Note Stop condition t SU;STO 2009.09 - Rev.A ...
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... BU8272GUW 2. GPIO･INT Interface The default mode of all GPIO [19:0] ports are input mode upon the power-on. By setting the specific bit of Interrupt Mask Sel register to “1”, the corresponding bit of Interrupt will be masked. There are two kinds of ways to control input / output operations. ...
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... BU8272GUW 2.1 Write to GPIO Port After setting the internal register address, the data from master is written from MSB. After Acknowledge is returned, the value of each GPIO port will be changed. ・IOSEL=1 In the condition that IOSEL register is “1”, after sending Acknowledge, a value “0” is output from the GPIO port which the corresponding bit is transferred as ‘ ...
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... BU8272GUW 2.2 Read From GPIO Port After slave address and R/W bit is written, the GPIO ports value will be read into the GPIO registers. (refer to section 8.1.6 for 2-wire reading protocol.) The data fixed between tow consecutive acknowledges will be transferred to the Master. SCL ...
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... BU8272GUW ● The Setting Registers When setting address is written beyond 00h~09h, the register address will be forced to value 00h. When the final address is set to 09h, then the next address 00h will be written. By making XRST “Low”, the setting register value will be initialed shown in following register map. ...
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... VDDIO2) must be connected to the voltage value defined in this specification, never left it open. 4. Caution of power on sequence The BU8272GUW can not works correctly even one of the power supply among the core power supply (VDD) and the I/O power supply ( VDDI2C, VDDIO1, VDDIO2) is not connected to specified conditions described in this specification. ...
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... BU8272GUW ●Ordering part number Part No. Part No. VBGA035W040 4.0 ± 0.1 1PIN MARK S 0. 0.75 ± 0.1 P=0.5×5 0.5 35- φ 0.295±0.05 φ 0. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved Package GUW: VBGA035W040 <Tape and Reel information> ...
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No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose ...