LTC2704-14 Linear Technology Corporation, LTC2704-14 Datasheet - Page 16

• Manufacturer Part Number: LTC2704-14
• Description: Ltc2704-14 - Quad 14-bit Voltage Output Softspan Dac With Readback
• Manufacturer: Linear Technology Corporation

OPERATIO
LTC2704
System Offset Adjustment
Many systems require compensation for overall system
offset, which may be an order of magnitude or more
greater than the excellent offset of the LTC2704.
The LTC2704 has individual offset adjust pins for each of
the four DACs. VOSA, VOSB, VOSC and VOSD are referred
to their corresponding signal grounds, AGNDA, AGNDB,
AGNDC and AGNDD. For noise immunity and ease of
adjustment, the control voltage is attenuated to the DAC
output:
The nominal input range of these pins is ±5V; other
reference voltages of up to ±15V may be used if needed.
The VOSx pins have an input impedance of 1MΩ. To
preserve the settling performance of the LTC2704, these
pins should be driven with a Thevenin-equivalent imped-
ance of 10kΩ or less. If not used, they should be shorted
to their respective signal grounds, AGNDx.
POWER-ON RESET AND CLEAR
When power is first applied to the LTC2704, all DACs
power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
are zero volts.
When the CLR pin is taken low, a system clear results. The
command and address shift registers, and the code and
configuration B2 buffers, are reset to 0; the DAC outputs
are all reset to zero volts. The B1 buffers are left intact, so
16
V
V
–2.5V to 7.5V spans]
V
OS
OS
OS
= –0.01 • V(VOSx) [0V to 5V, ±2.5V spans]
= –0.02 • V(VOSx) [0V to 10V, ±5V,
= –0.04 • V(VOSx) [±10V span]
U
that any subsequent “Update B1→B2” command (includ-
ing the use of LDAC) restores the addressed DACs to their
respective previous states.
If CLR is asserted during an operation, i.e., when CS/LD is
low, the operation is aborted. Integrity of the relevant input
(B1) buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low at
power-up, system clear, or if the logic supply V
below approximately 2V; and stays asserted until any valid
update command is executed.
SLEEP MODE
When a sleep command (C3 C2 C1 C0 = 1110) is issued,
the addressed DAC or DACs go into power-down mode.
DACs A and B share a reference inverting amplifier as do
DACs C and D. If either DAC A or DAC B (similarly for DACs
C and D) is powered down, its shared reference inverting
amplifier remains powered on. When both DAC A and
DAC B are powered down together, their shared reference
inverting amplifier is also powered down (similarly for
DACs C and D). To determine the sleep status of a
particular DAC, a direct read span command is performed
by addressing the DAC and reading its status on the
readback pin SRO. The fifth LSB is the sleep status bit (see
Figures 2a and 2b). Table 4 shows the sleep status bit’s
functionality.
Table 4. Readback Sleep Status Bit
SLP
0
1
STATUS
DAC n Awake
DAC n in Sleep Mode
DD
dips
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