APD-32A025A Vishay, APD-32A025A Datasheet - Page 3

• Manufacturer Part Number: APD-32A025A
• Description: Intelligent Plasma Display
• Manufacturer: Vishay

OPERATION PRINCIPLES
I/O Control
The I/O control section uses CS, A0, RD and WR lines to control data to and from the internal APD-32A025A registers and
buffers. The APD-32A025A has two 8-bit data registers (input and output) and an output busy flag F-F. All the data to and from
the APD-32A025A is enabled by CS.
The APD-32A025A input register is selected and written into by CS, A0 = 0 and WR. Note: 1 is not allowed for write
operation.
The master CPU can read either the APD-32A025A’s output register or the 1 bit busy flag. The output register is selected and
read by CS, A0 = 0 and RD. The busy flag is read (on data bus data bit 3) by CS, A0 = 1 and RD.
MASTER CPU AND APD-32A025A DATA TRANSFER INTERFACE
The APD-32A025A can be easily interfaced to any 8-bit microprocessor in a number of ways. The memory mapped I/O is the
simplest. The APD-32A025A is treated by the master CPU as a 2 location by 8-bit RAM. The master CPU can only write into
memory location “0”. It can read memory location “0” (data) or location “1” (busy flag).
The master CPU transfer commands to the APD-32A025A by writing into memory location “0”. Immediately after receiving any
command from the master CPU, the APD-32A025A will set the busy flag to “0” (data bus bit 3). The flag will remain “0” until the
APD-32A025A has executed the given command. The master CPU can test the flag by reading memory location “1” and
testing bit 3 for “1” (command execution finished). (All other bits are don’t cares.)
At the end of any “GET” command the output register will be loaded with the requested data. The master CPU may read the
output register at any time, however, the contents of the output will depend on the last completely executed “GET”
command.
Note that the EOC line provides a low pulse (900 ns min.) indicating the end of command execution. This line can be used to
set a flag or to interrupt the master CPU to indicate that the APD-32A025A has completed a command.
Document Number: 37081
Revision 24-May-05
READ OPERATION - OUTPUT AND FLAG REGISTER
WRITE OPERATION - INPUT REGISTER (A0 = 0)
DIMENSIONS (WAVEFORMS)
CS OR A
CS OR A
DATA BUS
(OUTPUT)
DATA BUS
(OUTPUT)
RD
RD
0
0
t AR
t AR
t AD
t AD
t RD
t RD
t RR
t RR
DATA VALID
DATA VALID
t RV
t RV
t RA
t RA
t RDF
t RDF
APD-32A025A
Vishay Dale
(READ CONTROL)
(READ CONTROL)
www.vishay.com
(SYSTEMS
ADDRESS BUS)
(SYSTEMS
ADDRESS BUS)
15