NP3665 Applied Micro Circuits Corporation (AMCC), NP3665 Datasheet - Page 3

• Manufacturer Part Number: NP3665
• Description: Oc-24 / 2ge Packet Processor For Mobile Infrastructure
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

nPcore Architecture
AMCC's software programmable nPcores are built from the ground
up for both packet- and cell-based networking data-plane
operations. The nP3665 supports up to OC-24 / 2-Gbps operation
utilizing one nPcore with 24 separate tasks which are all available for
either ingress or egress processing. The nPcore implements zero-
cycle task switching and zero-cycle branching for enhanced
performance.
The nPcore is surrounded by on-chip coprocessing engines to
accelerate sophisticated network processing functions, such as
packet classification, route and context searching, statistics
gathering, metering, policing, and packet transformations. The
nPcore, in combination with these on-chip coprocessing engines,
implements a Network Instruction Set Computing (NISC)
Architecture. This NISC architecture dramatically reduces the
number of lines of code required to implement many advanced
networking tasks.
A key addition to the fifth generation of NISC architecture is the
exception channel processing that provides flexibility in handling
packets that require increased processing time. This exception
channel handles special packets through a secondary path, without
affecting the deterministic line-rate performance of the regular
packets in the primary path. Another key addition to the fifth
generation architecture is the Channel Service Memory that enables
deep channelization in the line interfaces at all packet sizes and can
handle very large bursts in the incoming traffic without affecting
line-rate performance.
Single-Stage, Single-Image Programming
AMCC's nPcore architecture implements a simple single-stage
programming model. In this model, each cell or packet is processed
in its entirety, from start to finish, by a single task in the nPcore. With
this single-stage model, the entire data flow algorithm can be
created as a single complete software program, just as it would be
on a non-multiprocessor system, allowing the same program image
to be executed identically by each task of the nPcore. This approach
greatly simplifies programming while optimizing performance.
Traffic Management
The traffic management block in the nP3665 leverages AMCC’s
expertise and technology from the nPX5700 family of traffic
managers.
The nP3665 implements a hierarchical scheduling architecture to
provide multiple levels of bandwidth provisioning and per-
subscriber guarantees. This hierarchy consists of the following
logical levels: flow, pipe, subport, and port.
Additionally, the nP3665 expands the nP3700 Traffic Manager
hierarchy to support subflow Classes of Service functionality,
providing a fifth level of scheduling hierarchy for additional
service-level QoS flexibility. Minimum and maximum bandwidth
control can be configured on multiple levels. WFQ and Strict Priority
scheduling algorithms are also implemented by the traffic
management block. For ATM applications, non-real-time and
real-time CBR and VBR connections can be configured for a desired
subset of flows.
The nP3665 Traffic Manager is implemented in hardware for
guaranteed performance, unlike software-based traffic managers
that eat into the available instruction budget.
Input Admission Control
Sophisticated cell and packet admission controls are configurable in
the nP3665. This includes execution of standard discard
mechanisms such as WRED, EPD, and TPD in hardware, or the option
to perform variations in software.
Application Software
The nP3665 application software includes AAL2, AAL5, IPv4, and
IPv6 for mobile infrastructure access applications.
nP3665