LCP-8500A4EDR Delta Electronics, Inc., LCP-8500A4EDR Datasheet - Page 9

• Manufacturer Part Number: LCP-8500A4EDR
• Description: Rohs Compliant 8.5gb/s Short Wavelength Sfp+ Transceiver
• Manufacturer: Delta Electronics, Inc.

Timing parameters for SFP+ management
Notes:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10) From Occurrence of loss of signal to assertion of LOS.
11) From Occurrence of presence of signal to negation of RX_LOS.
DELTA ELECTRONICS, INC.
TX_DISABLE Assert time
TX_DISABLE Negate time
Time
interfase
Time to initialize
Time
module
Time to Power Up to Level 2
Time to Power Down from
Level 2
TX_Fault assert
TX_Fault assert for cooled
module
TX_Fault Reset
Module Reset
RS0, RS1 rate select timing
for FC
RS0, RS1 rate select timing
non FC
RX_LOS assert delay
RX_LOS negate delay
Rising edge of TX_Disable to fall of output signal below 10% of nominal.
Falling edge of TX_Disable to rise of output signal above 90% of nominal. This only applies in normal operation,
not during start up or fault recovery.
From power on or negation of TX_Disable.
From power on or TX_Disable negated during power up, or TX_Fault recovery, until non-cooled power level 1
part (or non-cooled power level 2 part already enabled at power level 2 for TX_Fault recovery) is fully operational.
From falling edge of stop bit enabling power level 2 until non-cooled module is fully operational.
From falling edge of stop bit disabling power level 2 until module is within power level 1 requirements.
From Occurrence of fault to assertion of TX_Fault.
Time TX_Disable must be held High to reset TX_Fault.
From assertion till stable output.
to
to
Parameter
initialize
initialize
cooled
2-wire
t_start_up_cooled
T_power_down
t_module_reset
t_power_level2
t_2w_start_up
t_RS0, t_RS1
TX_Fault_on
TX_Fault_on
t_RS0_FC,
t_start_up
RS1_FC
t_los_on
t_los_off
Symbol
t_reset
t_on
t_off
9
Min.
10
Max.
TBD
300
300
300
500
100
100
300
10
90
50
10
2
1
LCP-8500A4EDR
www.deltaww.com
msec
msec
msec
msec
msec
msec
msec
msec
msec
µsec
µsec
µsec
µsec
µsec
Unit
sec
Preliminary
2008/7/16
Note
TBD
10
11
1
2
3
4
4
5
6
7
7
8
9
9
Rev. 0A