MX25L3235D Macronix International Co., MX25L3235D Datasheet
MX25L3235D
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MX25L3235D Summary of contents
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... P/N: PM1383 MX25L3235D DATASHEET 1 MX25L3235D REV. 1.1, OCT. 14, 2008 ...
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... Sector Erase (SE) ..................................................................................................................................... 20 (11) Block Erase (BE) ...................................................................................................................................... 20 (12) Chip Erase (CE) ........................................................................................................................................ 21 (13) Page Program (PP) ................................................................................................................................... 21 (14 I/O Page Program (4PP) ...................................................................................................................... 22 (15) Continuously program mode (CP mode) ..................................................................................................... 22 (16) Deep Power-down (DP) ............................................................................................................................. 22 (17) Release from Deep Power-down (RDP), Read Electronic Signature (RES) ................................................. 23 P/N: PM1383 MX25L3235D Contents 2 REV. 1.1, OCT. 14, 2008 ...
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... Figure 22. Sector Erase (SE) Sequence (Command 20) .................................................................................. 38 Figure 23. Block Erase (BE) Sequence (Command D8) ................................................................................... 38 Figure 24. Chip Erase (CE) Sequence (Command 60 or C7) ............................................................................ 39 Figure 25. Deep Power-down (DP) Sequence (Command B9) .......................................................................... 39 Figure 26. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB P/N: PM1383 MX25L3235D 3 REV. 1.1, OCT. 14, 2008 ...
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... Figure 28. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command DF) ............. 40 Figure 29. Power-up Timing .............................................................................................................................. 41 Table 11. Power-Up Timing and VWI Threshold ................................................................................................. 41 INITIAL DELIVERY STATE ....................................................................................................................................... 41 RECOMMENDED OPERATING CONDITIONS .......................................................................................................... 42 ERASE AND PROGRAMMING PERFORMANCE ...................................................................................................... 43 LATCH-UP CHARACTERISTICS ............................................................................................................................... 43 ORDERING INFORMATION ...................................................................................................................................... 44 PART NAME DESCRIPTION ..................................................................................................................................... 45 PACKAGE INFORMATION ......................................................................................................................................... 46 REVISION HISTORY ................................................................................................................................................. 49 P/N: PM1383 MX25L3235D 4 REV. 1.1, OCT. 14, 2008 ...
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... Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) P/N: PM1383 MX25L3235D 32M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH 5 REV. 1.1, OCT. 14, 2008 ...
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... Hardware write protection or serial data Input/Output for 4 x I/O read mode • NC/SIO3 - NC pin or serial data Input/Output for 4 x I/O read mode • PACKAGE - 8-pin SOP (209mil) - 16-pin SOP (300mil) - 8-land WSON (6x5mm) - All Pb-free devices are RoHS Compliant P/N: PM1383 MX25L3235D 6 REV. 1.1, OCT. 14, 2008 ...
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... The MX25L3235D are 32,554,432 bit serial Flash memory, which is configured as 4,194,304 x 8 internally. When two or four I/O read mode, the structure becomes 16,777,216 bits 8,388,608 bits x 4. The MX25L3235D feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO) ...
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... WP#/SIO2 SO/SIO1 9 8-LAND WSON (6x5mm) 1 VCC CS NC/SIO3 SO/SIO1 7 3 SCLK WP#/SIO2 6 4 SI/SIO0 GND 4 P/N: PM1383 MX25L3235D 8-PIN SOP (200mil) CS SO/SIO1 7 3 WP#/SIO2 6 GND 4 5 PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O)/ Serial Data Input & ...
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... BLOCK DIAGRAM SI/SIO0 CS# WP#/SIO2 NC/SIO3 SCLK SO/SIO1 P/N: PM1383 Address Generator Memory Array Page Buffer Data Register SRAM Buffer Mode State Logic Machine Generator Clock Generator 9 MX25L3235D Y-Decoder Sense Amplifier HV Output Buffer REV. 1.1, OCT. 14, 2008 ...
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... DATA PROTECTION The MX25L3235D is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences ...
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... Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed. Table 3. 4K-bit Secured OTP Definition Address range Size xxx000~xxx00F 128-bit xxx010~xxx1FF 3968-bit P/N: PM1383 Protect Level 32Mb Standard Factory Lock ESN (electrical serial number) N/A 11 MX25L3235D Customer Lock Determined by customer REV. 1.1, OCT. 14, 2008 ...
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... MX25L3235D Address Range Sector 767 2FF000h 2FFFFFh . . . . . . . . . 752 2F0000h 2F0FFFh 751 2EF000h 2EFFFFh . . . . . . . . . 736 2E0000h 2E0FFFh 735 2DF000h 2DFFFFh . . . . . . . . . 720 2D0000h 2D0FFFh 719 2CF000h 2CFFFFh ...
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... MX25L3235D Address Range 255 0FF000h 0FFFFFh . . . . . . . . . 240 0F0000h 0F0FFFh 239 0EF000h 0EFFFFh . . . . . . . . . 224 0E0000h 0E0FFFh 223 0DF000h 0DFFFFh . . . . . . . . . 208 0D0000h 0D0FFFh 207 0CF000h 0CFFFFh . . ...
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... CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1383 shift in MSB 14 MX25L3235D shift out MSB REV. 1.1, OCT. 14, 2008 ...
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... ID & device secured secured security ID OTP OTP m ode register m ode 15 MX25L3235D 2RE 4RE (fas t x I/O read x I/O read read data and and) Note1 0B (hex ) B B (hex ) E B (hex ) DD(2) A DD(4) & ...
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... RDID operation can use CS# to high at any time during data out. (see Figure 11.) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage. P/N: PM1383 MX25L3235D 16 REV. 1.1, OCT. 14, 2008 ...
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... Enable 1= status (note1) register write 0=not Quad Enable disable Non- volatile bit Non- volatile bit Non- volatile bit Note 1: see the table 2 "Protected Area Size" in page 11. P/N: PM1383 MX25L3235D bit4 bit3 bit2 BP2 BP1 BP0 (level of (level of (level of protected block) protected block) ...
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... If SRWD bit=1 but WP#/SIO2 is low impossible to write the Status Register even if the WEL bit has previously been set rejected to write the Status Register and not be executed. P/N: PM1383 MX25L3235D WP# and SRWD bit status WP#=1 and SRWD bit=0, or The protected area cannot WP#=0 and SRWD bit= program or erase ...
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... CS# to high at any time during data out (see Figure 16 for 2 x I/O Read Mode Timing Waveform). While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. P/N: PM1383 MX25L3235D 19 REV. 1.1, OCT. 14, 2008 ...
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... The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K- byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before P/N: PM1383 MX25L3235D 20 REV. 1.1, OCT. 14, 2008 ...
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... Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected P/N: PM1383 MX25L3235D 21 REV. 1.1, OCT. 14, 2008 ...
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... SO pin outputs tri-state if CS# goes high. DSRY (disable SO to output RY/BY#) instruction to disable the SO to output RY/BY# and return to status register data output during CP mode. Please note that the ESRY/DSRY command are not accepted unless the completion of CP mode. (16) Deep Power-down (DP) P/N: PM1383 MX25L3235D 22 REV. 1.1, OCT. 14, 2008 ...
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... Table of ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high. P/N: PM1383 MX25L3235D 23 REV. 1.1, OCT. 14, 2008 ...
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... While 4K-bit secured OTP mode, array access is not allowed. Continuously Program Mode( CP mode) bit. The Continuously Program Mode bit indicates the status of CP mode, "0" indicates not in CP mode; "1" indicates in CP mode. P/N: PM1383 MX25L3235D MX25L3235D Memory type Memory Density 5E 16 ...
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... Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more. The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high. The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. P/N: PM1383 MX25L3235D bit4 bit3 bit2 Continuously ...
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... At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might occur during the stage while a write, program, erase cycle is in progress. P/N: PM1383 MX25L3235D 26 REV. 1.1, OCT. 14, 2008 ...
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... Figure 2.Maximum Negative Overshoot Waveform 20ns 0V -0.5V CAPACITANCE TA = 25° 1.0 MHz SYMBOL PARAMETER CIN Input Capacitance COUT Output Capacitance P/N: PM1383 MX25L3235D VALUE -40° 85° C for Industrial grade -55° 125° C -0.5V to 4.6V -0.5V to 4.6V -0.5V to 4.6V Figure 3. Maximum Positive Overshoot Waveform 4.6V 3.6V MIN. TYP MAX ...
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... Figure 5. OUTPUT LOADING DEVICE UNDER TEST CL=30pF Including jig capacitance (CL=15pF Including jig capacitance for 104MHz, 75MHz@2xI/O and 75MHz@4xI/O) P/N: PM1383 MX25L3235D Output timing referance level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <5ns 2.7K ohm CL 6 ...
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... V 0.7VCC VCC+0.4 V 0.4 V VCC-0 MX25L3235D TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VIN = VCC or GND CS# = VCC VIN = VCC or GND CS# = VCC f=104MHz fQ=75MHz (4 x I/O read) SCLK=0.1VCC/0.9VCC, SO=Open f=66MHz fT=75MHz (2 x I/O read) SCLK=0 ...
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... Value guaranteed by characterization, not 100% tested in production. 3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set Test condition is shown as Figure 4, 5. P/N: PM1383 MX25L3235D Min. Typ. D.C. D. ...
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... Timing Analysis Figure 6. Serial Input Timing CS# tCHSL SCLK tDVCH SI High-Z SO Figure 7. Output Timing CS# SCLK tCLQV tCLQX tCLQX SO ADDR.LSB IN SI P/N: PM1383 tSLCH tCHSH tCHDX tCLCH MSB LSB tCH tCLQV tCL tQLQH tQHQL 31 MX25L3235D tSHSL tSHCH tCHCL tSHQZ LSB REV. 1.1, OCT. 14, 2008 ...
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... Figure 9. Write Enable (WREN) Sequence (Command 06) CS# SCLK SI SO Figure 10. Write Disable (WRDI) Sequence (Command 04) CS# SCLK SI SO P/N: PM1383 Command 06 High Command 04 High-Z 32 MX25L3235D tSHWL REV. 1.1, OCT. 14, 2008 ...
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... MSB MSB command Status Register MSB High-Z 33 MX25L3235D Device Identification Status Register Out REV. 1.1, OCT. 14, 2008 ...
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... BIT ADDRESS DATA OUT MSB 34 MX25L3235D Data Out 1 Data Out DATA OUT MSB MSB REV ...
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... SCLK 8 Bit Instruction EB(hex) SI/SIO0 High Impedance SO/SIO1 High Impedance WP#/SIO2 High Impedance NC/SIO3 P/N: PM1383 MX25L3235D dummy 12 BIT Address cycle address dummy bit6, bit4, bit2...bit0, bit6, bit4.... bit22, bit20, bit18...bit0 address dummy bit23, bit21, bit19 ...
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... P4 P0 bit4, bit0, bit4.... data P5 P1 bit5 bit1, bit5.... data P6 P2 bit6 bit2, bit6.... data P7 P3 bit7 bit3, bit7.... 36 MX25L3235D n Data Output data bit4, bit0, bit4.... data bit5 bit1, bit5.... data bit6 bit2, bit6.... data bit7 bit3, bit7.... REV. 1.1, OCT. 14, 2008 ...
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... Command 6 Address cycle MX25L3235D Data Byte MSB Data Byte 256 MSB ...
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... Byte 0, Byte1 status ( Command 24 Bit Address MSB Command 24 Bit Address MSB 38 MX25L3235D data in 04 (hex) 05 (hex REV. 1.1, OCT. 14, 2008 ...
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... DP Command B9 Stand-by Mode Dummy Bytes MSB Electronic Signature Out MSB Deep Power-down Mode 39 MX25L3235D Deep Power-down Mode RES2 Stand-by Mode REV. 1.1, OCT. 14, 2008 ...
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... Dummy Bytes Manufacturer MSB MSB 40 MX25L3235D Stand-by Mode 47 Device MSB REV. 1.1, OCT. 14, 2008 ...
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... The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1383 Chip Selection is Not Allowed tVSL Read Command is tPUW 41 MX25L3235D Device is fully allowed accessible time Min. Max. Unit ...
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... For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1383 tCHSL tSLCH tDVCH tCHDX MSB IN High Impedance Figure A. AC Timing at Device Power-Up Notes 1 42 MX25L3235D tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN Min. Max. Unit 20 500000 us/V ...
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... The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=3.0V, and 100K cycle with 90% confidence level. LATCH-UP CHARACTERISTICS Input Voltage with respect to GND on all power pins, SI, CS# Input Voltage with respect to GND on SO Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1383 MX25L3235D Min. TYP. (1) Max. (2) 40 100 60 300 ...
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... ORDERING INFORMATION PART NO. CLOCK (MHz) MX25L3235DMI-12G 86 MX25L3235DM2I-12G 86 MX25L3235DM2I-10G 104 MX25L3235DMI-10G 104 MX25L3235DZNI-10G* 104 *Advanced information P/N: PM1383 OPERATING STANDBY Temperature PACKAGE Remark CURRENT MAX. CURRENT MAX. (mA) (uA -40° C~85° C 16-SOP 25 20 -40°C~85° -40°C~85° -40°C~85° -40°C~85°C ...
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... PART NAME DESCRIPTION P/N: PM1383 3235D OPTION: G: Pb-free SPEED: 12: 86MHz 10: 104MHz TEMPERATURE RANGE: I: Industrial (-40° 85° C) PACKAGE: ZN: WSON M: 300mil 16-SOP M2: 200mil 8-SOP DENSITY & MODE: 3235D: 32Mb standard type TYPE DEVICE: 25: Serial Flash 45 MX25L3235D REV. 1.1, OCT. 14, 2008 ...
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... PACKAGE INFORMATION P/N: PM1383 MX25L3235D 46 REV. 1.1, OCT. 14, 2008 ...
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... P/N: PM1383 MX25L3235D 47 REV. 1.1, OCT. 14, 2008 ...
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... P/N: PM1383 MX25L3235D 48 REV. 1.1, OCT. 14, 2008 ...
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... Modified the sector erase typical time from 60ms to 90ms 7. Modified Low Vcc write inhibit: from 1.5V to 2.5V 1.1 1. Revised sector erase time spec from 90ms(typ.) to 60ms(typ.) 2. Modified 4xI/O Read Mode (4READ) description regarding performance-enhancing mode P/N: PM1383 MX25L3235D Page P1 P5 P15 P44 P45 P30 ...
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... Macronix Europe N.V. Koningin Astridlaan 59, Bus 1 1780 Wemmel Belgium Tel: +32-2-456-8020 Fax: +32-2-456-8021 Singapore Office Macronix Pte. Ltd. 1 Marine Parade Central #11-03 Parkway Centre Singapore 449408 Tel: +65-6346-5505 Fax: +65-6348-8096 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 50 MX25L3235D ...