MB86605 Fujitsu Microelectronics, Inc., MB86605 Datasheet
MB86605
Related parts for MB86605
MB86605 Summary of contents
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... Due to this, all the SCSI bus sequences including the data transfer can be performed automatically. As the system interface block, it incorporates a 32-bit PCI local bus interface which makes MB86605 an ideal “on-board PCI-SCSI controller” as well as a “host adapter” for PCs, servers and work stations. It also supports 16-bit separate MPU and DMA buses ...
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... MB86605 FEATURES SCSI Protocol Controller Block: • Operable as initiator and target • WIDE and FAST data transfer – Synchronous transfer (max. 20 Mbytes/ offset values can be set.) – Asynchronous transfer (max. 10 Mbytes/s) • 64-byte FIFO register for data phase • Two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases (MCS Buffers) • ...
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... Data Bus Parity and Address Bus Parity (only for PCI bus interface mode) generation/check function Others • Compact 144-Pin Plastic Low Profile Shrink Quad Flat Package (LQFP , Package Suffix: –PMT) • Pin compatible with MB86606 • Supply Voltage ±5% MB86605 3 ...
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... MB86605 PIN ASSIGNMENT • 16-Bit Bus Mode DMD9 DMD8 DMD7 5 DMD6 V DD INDEX DMD5 V SS DMD4 10 DMD3 DMD2 V SS DMD1 DMD0 15 LDMDP V SS UDP V DD D15 20 D14 V SS D13 D12 D11 D10 ...
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... V SS PERR PAR C/BE1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 (TOP VIEW) (FPT-144P-M08) MB86605 LDBOEP V DD DB12 105 DB13 DB14 DB15 V SS UDBP 100 DB0 DB1 V SS DB2 DB3 95 DB4 DB5 V SS DB6 DB7 90 LDBP ...
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... MB86605 PIN LIST 16-bit bus mode Pin no. Mode 0 (68 I/F) Mode 1 (80 I/F) I/O Pin name I/O Pin name I/O Pin name 1 I/O DMD9 2 — I/O DMD8 4 I/O DMD7 5 I/O DMD6 6 — I/O DMD5 8 — I/O DMD4 10 I/O DMD3 11 I/O DMD2 12 — I/O DMD1 14 I/O DMD0 15 I/O LDMDP 16 — I/O UDP 18 — ...
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... I/O DB13 106 I/O DB12 107 — 108 O LDBOEP 109 O DBOE7 110 O DBOE6 111 O DBOE5 112 — 113 O DBOE4 114 O DBOE3 115 O DBOE2 116 — 117 O DBOE1 118 O DBOE0 119 O UDBOEP 120 O DBOE15 MB86605 PCI bus I/F mode Mode 3 (PCI I/F) (Continued) 7 ...
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... MB86605 (Continued) 16-bit bus mode Pin no. Mode 0 (68 I/F) Mode 1 (80 I/F) I/O Pin name I/O Pin name I/O Pin name 121 O DBOE14 122 — 123 O DBOE13 124 O DBOE12 125 I DMA0 126 I TP 127 I RESET 128 — 129 I DACK 130 O DREQ 131 — ...
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... When CS0 input valid: I/O ports for internal registers in SPC When CS1 input valid: I/O ports for DMA bus data I/O Lower byte and parity of data bus When CS0 input valid: I/O ports for internal registers in SPC When CS1 input valid: I/O ports for DMA bus data MB86605 (Continued) 9 ...
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... MB86605 (Continued) Pin no. Pin name 51, 52 (R/ (LDS) 42 BHE (UDS) 3. 16-Bit Bus Mode – DMA Interface Pin no. Pin name 130 DREQ 129 DACK 138, 139, 141 to 144 DMD15 to 8 136 UDMDP 11, 13, 14 DMD7 to 0 ...
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... I This is a chip select signal that indicates the configuration access. I PCI bus clock input pin. The maximum clock frequency is 33 MHz. I/O Data parity error input and output pin. OD Address parity error output pin. MB86605 ). DD 11 ...
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... MB86605 5. Other Signals Pin no. Pin name 127 RESET 59, 60 MODE1, MODE0 50 INT 6, 18, 31, 43, 49, 63 73, 107, 116, 131, 137 2, 8, 12, 16, 21, 25 30, 35, 40, 45, 53, 58, 66, 77, 82, 88, 93, 98, 102, 112, 122, 128, 134, 140 51, 52 PO1, PO0 55, 56 PI1, PI0 57 N ...
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... Bytes) Receive MSG, CMD, Status Buffer 7 (32 Bytes) Send MSG, CMD, Status Buffer 8 (2048 Bytes) User Program Memory (64 Bytes) 9 (512 Bytes) Data Register MB86605 DREQ DACK DMBHE (DMUDS) DMA0 DMD15 to 8, UDMAP DMD7 to 0, LDMDP IOWR (DMLDS) IORD (DMR/ ...
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... MB86605 2. PCI Bus Interface Mode MSG C/D I/O ATN BSYOE BSY SELOE SEL RSTOE RST REQ ACK INIT TARG DB15 to 8, UDBP DB7 to 0, LDBP DBOE15 to 8, UDBOEP DBOE7 to 0, LDBOEP S/DSEL 14 PCI Interface 1 5 Internal Various Processor Registers 2 Timer 6 (32 Bytes) Receive ...
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... Interrupt status register This register indicates the interrupt status with an 8-bit code. : Time required for initiator to assert ACK signal after asserting REQ signal : Time required for target to negate REQ signal after asserting ACK signal 0 from initiator after sending REQ signal MB86605 15 ...
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... MB86605 • Command step register This register indicates the execution status of each command with an 8-bit step code. Error causes can be analyzed by referencing the interrupt status register and this register. • Group 6/7 command length setting register This register sets the group 6/7 command length not defined in the SCSI standard. ...
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... Rating Symbol Min – 0 – 0 – 0 Top –25 Tstg –40 Value Symbol Min. Typ. V 4.75 5 20.0 — SCSI f — — PCI Ta 0 — MB86605 Unit Max +85 +125 C Unit Max. 5.25 V 40.0 MHz 33.0 MHz + ...
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... MB86605 ELECTRICAL CHARACTERISTICS 1. DC Characteristics Parameter SCSI pins Input SCLK pins voltage * 1 SDSEL pins Other pins 1 SCSI-pin input hysteresis * REQ, ACK RST, BSY, SEL In single- end mode SCSI pins Others Output voltage * 1 In differential mode PCI bus interface pins Other pins ...
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... DMD15 to DMD8, UDMDP, DMD7 to DMD0, LDMDP PCI bus interface mode C L Pin name PCI bus pins ( V±5 Load resistance Load capacitance MB86605 = MHz + Value Unit Min. Max. — — — — ...
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... MB86605 4. AC Characteristics (1) System clock • SCSI clock (SCLK pin) Parameter Clock period Clock pulse width (Low) Clock pulse width (High) Clock pulse rise time Clock pulse fall time Note: When the internal operating clock frequency is the same as the input clock frequency, (when using the device in divide-by-1 mode), the clock pulse width for L and H levels must have minimum 20 ...
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... Typ. t 30.0 — PCY t 12.0 — PLO t 12.0 — PHI t 1.0 — PSR V – V 2.0 — IHP ILP t PCY 2.0 V 2.0 V 0 PLO Value Symbol Min. Typ — WRSL CLF t WRSL MB86605 Unit Max. — ns — ns — ns 4.0 V/ns — IHP 2 ILP Unit Max. — ...
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... MB86605 5. MPU Interface (1) Register write timing for 80 series Parameter Address (A4 to A0), BHE set up time Address (A4 to A0), hold time CS0 set up time CS0 hold time Data set up time Data hold time WR “L” level pulse width BHE CS0 WR D15 to 8, UDP ...
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... ARH t 20 CRS t 10 CRH t — RLD t 5 RHD — — DL2 ARS t t CRS RD t RLD Valid data t DL MB86605 Value Unit Max. — ns — ns — ns — — ns — CLF t ARH t CRH t RHD * t ...
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... MB86605 (3) Register write timing for 80 series (for external access) Parameter Address (A0), BHE set up time Address (A0), BHE hold time CS1 set up time CS1 hold time WR set Low DMA bus output delay time WR set High DMA bus output undefined time MPU data bus ...
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... D15 to 8, UDP LDP Value Symbol Min ARSE t 20 ARHE t 20 CRSE t 10 CRHE t — RLNZ t 5 RHHZ t — HDD t ARHE t CRHE Data t HDD t t RLNZ RHHZ Valid data MB86605 Unit Max. — ns — ns — ns — — ...
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... MB86605 (5) Register write timing for 68 series Parameter Address (A4 to A0) set up time Address (A4 to A0) hold time CS0 set up time CS0 hold time Data set up time Data hold time UDS/LDS “L” level pulse width R/W set up time R/W hold time CS0 R/W UDS/LDS D15 to 8, UDP ...
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... RLD t 5 RHD RWS t 20 RWH t — — DH2 t ARS t CRS t t RWS DS t RLD Valid data t DH MB86605 Value Unit Max. — ns — ns — ns — — ns — ns — ns — CLF t ARH t CRH t ...
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... MB86605 (7) Register write timing for 68 series (for external access) Parameter Address (A0) set up time Address (A0) hold time CS1 set up time CS1 hold time UDS/LDS set Low DMA bus output delay time UDS/LDS set High DMA bus output undefined time MPU data bus ...
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... D15 to 8, UDP LDP Symbol Min. t ARSE t ARHE t CRSE t CRHE t RLNZ t RHHZ t HDD t RWS t RWH t ARSE t CRSE t RWS t HDD t RLNZ MB86605 Value Unit Max. 40 — — — — ns — — ns — — — ARHE ...
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... MB86605 6. DMA Interface DMA access timing The time regulations are not applicable in the following cases: • During SCSI input and when data buffer EMPTY, or when one byte held • During SCSI output and when data buffer FULL, or when 63 bytes held • When parity error detected (target) • ...
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... DLDH t 0 ALWL t 20 DAWS t 40 DWR t 0 WHAH t 20 DAWH t 30 DDWS t 10 DDWH t t ALDL t ALWL t t DAWS DWR t DDWS Data MB86605 Value Unit Max. — — ns — ns — ns — ns — ns — ns — ns — ns DLDH t WHAH t DAWH t DDWH 31 ...
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... MB86605 (3) Read timing (burst mode for 80 series) Parameter DREQ set High DACK set Low IORD set Low DREQ set Low DREQ set Low DREQ set High DACK set Low IORD set Low DMBHE, DMA0 set up time IORD “L” level pulse width ...
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... DLDH t 10 ALDL t 20 DRWS t 40 DDS t 0 DHAH t 20 DRWH t 30 DDWS t 10 DDWH t t ALDL t ALDL t t DRWS DDS t DDWS Data MB86605 Value Unit Max. — — ns — ns — ns — ns — ns — ns — ns — ns DLDH t DHAH t DRWH t DDWH 33 ...
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... MB86605 (5) Read timing (burst mode for 68 series) Parameter DREQ set High DACK set Low DMUDS/DMLDS set Low DREQ set Low DREQ set Low DREQ set High DACK set Low DMUDS/DMLDS set Low R/W set up time DMUDS/DMLDS “L” level pulse width DMUDS/DMLDS set High ...
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... Applicable to GNT pin PCICLK OUTPUT OUTPUT H/L to Hi-Z OUTPUT Hi-Z to H/L INPUT Symbol Min PVAL t — POFF t 2 PON t 7/ PSU t 0 PHD 1 PVAL t POFF t PON 1 PSU PHD MB86605 Value Unit Max 11/ — ns — ns — ns 2.4 V 0.4 V 2 ...
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... MB86605 (2) Configuration register read timing PCICLK FRAME IDSEL AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP (3) Configuration register write timing PCICLK FRAME IDSEL AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP Note: For the access to the configuration register, only one data transfer possible. ...
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... BASIC control register read timing (target mode) • Byte or word access Burst read (target termination), single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP MB86605 37 ...
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... MB86605 • Long-word access Single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP Burst read (target termination) PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP Note: For the read operation of BASIC control registers, only one data transfer possible. ...
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... Target mode–I/O, memory read timing (except BASIC control registers) • Byte, word access Single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL MB86605 39 ...
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... MB86605 • Long-Word access Single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 40 ...
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... Target Mode–I/O, memory write timing • Byte, word access Single write burst write PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL MB86605 41 ...
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... MB86605 • Long-word access Single write PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst write PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 42 ...
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... Data read timing (master mode) • Burst length = PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL • Burst length = 8 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL • Burst length = 16 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL MB86605 43 ...
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... MB86605 (8) Data write timing (master mode) • Burst length = PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL • Burst length = 8 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL • Burst length = 16 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY ...
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... AOHR t 10 DTSU t 20 DHLD t — RAOL t — RACY + t RAOH * t RACY AOLR RAOH AOHR t t DIVD Valid data MB86605 Unit Max. — — ns — ns — CLF + itself. AOHR RAOL RACY t RAOL DVLD Valid data 45 ...
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... MB86605 (2) Initiator asynchronous output timing (initiator Parameter ACK set Low REQ set High REQ set High ACK set High ACK set High REQ set Low Data bus output defined ACK set Low* REQ set High data bus hold time REQ set Low ACK set Low * : The value of S varies with the setting condition of the asynchronous set up time register (address 17h) ...
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... RQAP REQ Symbol Min • t – 12 AKAP CLF t N • t ANAP CLF t 20 RQAP t 20 RNAP RQF1 CLF RQF2 CLF t t AKAP ANAP t RNAP t RQF1 t RQF2 MB86605 Value Unit Max. — — ns — ns — ns — ns — ...
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... MB86605 (4) Initiator synchronous transfer input timing (target Parameter Data bus defined REQ set Low REQ set Low data bus hold time REQ DB7 DB15 (5) Initiator synchronous transfer output timing (initiator Parameter Data bus defined ACK set Low* ACK set Low data bus hold time The vales of A and N vary with the setting condition of the transfer period register (address 0Dh) ...
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... AROH t 0 ROHA t 10 DTSU t 20 DHLD t — AROL t — RACY AROH t RACY t AROH t t ROLA ROHA t t DTSU DHLD Data MB86605 Value Unit Max. — — ns — ns — CLF + itself. ROHA AROL RACY t AROL 49 ...
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... MB86605 (7) Target asynchronous output timing (target Parameter REQ set Low ACK set Low ACK set Low REQ set High REQ set High ACK set High Data bus defined REQ set Low* ACK set Low data bus hold time ACK set High REQ set Low * : The value of S varies with the setting condition of the asynchronous set up time register (address 17h) ...
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... REQ ACK Symbol Min • t – 12 RQAP CLF t N • RNAP CLF t 20 AKAP t 20 ANAP AKF1 CLF AKF2 CLF t RNAP t t AKAP ANAP t AKF1 t AKF2 MB86605 Value Unit Max. — ns — ns — ns — ns — ns — ...
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... MB86605 (9) Target synchronous transfer input timing (initiator Parameter Data bus defined ACK set Low ACK set Low data bus hold time REQ DB7 DB15 (10) Target synchronous transfer output timing (target Parameter Data bus defined REQ set Low* REQ set Low data bus hold time The values of A and N vary with the setting condition of the transfer period register (address 0Dh) ...
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... MB86605 ...
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... MB86605 • Set value for asynchronous set up time register and S value Asynchronous set up time register Note: The S (set up time) value of the set up time setting register in asynchronous data transfer represents the time required to assert the REQ or ACK signal after setting data at the data bus (in clock-cycle units) ...
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... LDP C/D BHE I DR/REV TARG DMD15 to 0 UDMDP LDMDP BSY BSYOE DREQ SEL DACK SELOE DMBHE I ORD I OWR RST RSTOE DMA0 TP SDSEL OSC MPU ADDRESS DECODE ADDRESS BUS DATA BUS DMA BUS DMA ADDRESS CONTROL MB86605 RESET circuit DATA BUFFER MEMORY 55 ...
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... MB86605 2. 68-Series Separate Bus Type MB86606 DB15 to 8 RESET UDBP DB7 to 0 MODE0 LDBP MODE1 DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP DIFFERENTIAL ACK ATN INIT REQ D15 to D0 MSG UDP C/D I/O UDS DR/REV TARG DMD15 to 0 UDMDP LDMDP BSY BSYOE DREQ ...
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... D15 to D0 MSG UDP LDP C/D BHE I DR/REV TARG DMD15 to 0 UDMDP LDMDP BSY BSYOE DREQ SEL DACK SELOE DMBHE I ORD I OWR RST RSTOE DMA0 TP SDSEL OSC MPU ADDRESS DECODE ADDRESS BUS DATA BUS DMA BUS DMA CONTROL MB86605 RESET circuit 57 ...
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... MB86605 4. 68-Series Common Bus Type MB86606 DB15 to 8 RESET LDBP DB7 to 0 MODE0 UDBP MODE1 DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP DIFFERENTIAL ACK ATN INIT REQ D15 to D0 MSG UDP C/D I/O UDS DR/REV TARG DMD15 to 0 UDMDP LDMDP BSY BSYOE DREQ ...
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... REQ, MSG C/D, I/O TARG BSY, SEL RST BSYOE, SELOE RSTOE SDSEL (TOP VIEW DO DO GND MB561 MB86605 (+) SIGNAL (–) SIGNAL (+) SIGNAL (–) SIGNAL SCS (+) SIGNAL (–) SIGNAL (+) SIGNAL (–) SIGNAL 59 ...
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... MB86605 6. Example of Connection in Single-end Mode MB86606 DB15 to 0 UDBP LDBP DBOE15 to 0 UDBOEP LDBOEP ACK, ATN INIT REQ, MSG C/D, I/O TARG BSY, SEL RST BSYOE, SELOE RSTOE SDSEL (OPEN) 2 (OPEN) 4 (OPEN (OPEN ...
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... ORDERING INFORMATION Part number MB86605PMT Package 144-pin Plastic LQFP (FPT-144P-M08) MB86605 Remarks 61 ...
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... MB86605 PACKAGE DIMENSION 144-pin Plastic LQFP (FPT-144P-M08) 62 ...
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... MEMO MB86605 63 ...
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... MB86605 Worldwide Headquarters Japan Fujitsu Limited Tel: +81 44 754 3753 4-1-1 Kamiodanaka Fax: +81 44 754 3332 Nakahara-ku, Kawasaki-shi. Kanagawa 211-88 Japan http://www.fujitsu.co.jp/ USA Tel: +1 408 922 9000 Fujitsu Microelectronics Inc Fax: +1 408 922 9179 3545 North First Street San José CA 95134-1804 ...