ES3207 ESS Technology, Inc., ES3207 Datasheet - Page 3

• Manufacturer Part Number: ES3207
• Description: Video Cd/dvd Companion Chip, 5 V
• Manufacturer: ESS Technology, Inc.

ES3207 VIDEO CD CC PRODUCT BRIEF
PIN DESCRIPTION
ESS Technology, Inc.
Name
TSD
TBCK
RWS
SEL_PLL1
RSTOUT#
NC
RSD
SEL_PLL0
RBCK
SER_IN
VSSA
VREFM
VREFP
VCCA
AOR
AOL
MIC2
MIC1
VREF
VCM
RSET
COMP
CDAC
YDAC
VDAC
XOUT
XIN
PCLK
PCLK2X
HSYNC#
VSYNC#
YUV[7:0]
41,50:51,56:57,62:63
86:89,92,94,96,98
27:28,65:76
44:45,59:60
Number
21
22
23
24
33
37
42
43
46
47
48
49
52
53
54
55
58
61
64
71
74
79
80
82
84
I/O Definition
I/O 13.5 MHz pixel clock.
I/O 27 MHz (2 times pixel clock).
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Transmit audio data input.
Transmit audio bit clock.
Dual-purpose pin. RWS is the receive audio frame sync.
Pins SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
Reset output (active-low).
No connect. Do not connect to these pins.
Dual-purpose pin. RSD is the receive audio data input.
SEL_PLL0 along with SEL_PLL1 select the PLL clock frequency for the DCLK out-
put. See the table for pin number 23.
Dual-purpose pin. RBCK is the receive audio bit clock.
SER_IN is the serial input DSC mode.
0 = Parallel DSC mode.
1 = Serial DSC mode.
Analog ground.
DAC and ADC minimum reference. Bypass to VCMR with 10 F in parallel with 0.1 F.
DAC and ADC maximum reference. Bypass to VCMR with 10 F in parallel with 0.1 F.
Analog VCC, 5 V.
Right channel output.
Left channel output.
Microphone input 2.
Microphone input 1.
Internal resistor divider generates Common Mode Reference (CMR) voltage.
Bypass to analog ground with 0.1 F.
ADC Common Mode Reference (CMR) buffer output. CMR is approximately 2.25 V.
Bypass to analog ground with 47 F electrolytic in parallel with 0.1 F.
Full scale DAC current adjustment.
Compensation pin.
Modulated chrominance output.
Y luminance data bus for screen video port.
Composite video output.
Crystal output.
27 MHz crystal input.
Horizontal sync (active-low).
Vertical sync (active-low).
YUV data bus for screen video port.
SEL_PLL1
0
0
1
1
SEL_PLL0
0
1
0
1
DCLK
Bypass PLL (input mode)
27 MHz (output mode)
32.4 MHz (output mode)
40.5 MHz (output mode)
SAM0076-051701
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