S3032 AMCC (Applied Micro Circuits Corp), S3032 Datasheet

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S3032

Manufacturer Part Number
S3032
Description
Sonet/sdh/atm OC-3/12 Transceiver W/cdr
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

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Part Number:
S3032A
Manufacturer:
AMCC
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S3032QF
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FEATURES
APPLICATIONS
Figure 1. System Block Diagram
DEVICE
SPECIFICATION
SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
BiCMOS LVPECL CLOCK GENERATOR
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
• Complies with Bellcore and ITU-T
• On-chip high-frequency PLL for clock
• Supports 155.52 Mbps (OC-3) and 622.08
• Selectable reference frequencies of 19.44,
• Interface to both LVPECL and TTL logic
• 8-bit TTL data path
• Compact 10 mm 64 PQFP/TEP package
• Diagnostic loopback mode
• Low jitter LVPECL interface
• Single 3.3V supply
• SONET/SDH-based transmission systems
• SONET/SDH modules
• SONET/SDH test equipment
• ATM over SONET/SDH
• Section repeaters
• Add Drop Multiplexers (ADM)
• Broad-band cross-connects
• Fiber optic terminators
• Fiber optic test equipment
specifications
generation
Mbps (OC-12)
38.88, 51.84 or 77.76 MHz
Processor
Network
Interface
8
8
SONET/SDH
Transceiver
S3033
S3024
OTX
ORX
GENERAL DESCRIPTION
The S3033 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET OC-12
(622.08 Mbps) and OC-3 (155.52 Mbps) interface de-
vice. The chip performs all necessary serial-to-parallel
and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure 1
shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3033
transceiver chip allowing the use of a slower external
transmit clock reference. The S3033 performs
SONET/SDH frame detection. The chip can be used
with 19.44, 38.88, 51.84 or 77.76 MHz reference
clocks, in support of existing system clocking
schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3033 is pack-
aged in a 10 mm 64 PQFP/TEP, offering designers a
small package outline.
ORX
OTX
S3024
SONET/SDH
Transceiver
S3033
8
8
Processor
Interface
Network
S3033
S3033
S3033
®
1

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S3032 Summary of contents

Page 1

DEVICE SPECIFICATION SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER BiCMOS LVPECL CLOCK GENERATOR SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER FEATURES • Complies with Bellcore and ITU-T specifications • On-chip high-frequency PLL for clock generation • Supports 155.52 Mbps (OC-3) and 622.08 Mbps ...

Page 2

S3033 SONET OVERVIEW Synchronous Optical Network (SONET stan- dard for connecting one fiber system to another at the optical level. SONET, together with the Synchro- nous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard ...

Page 3

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER Figure 4. S3033 Transceiver Functional Block Diagram Transmitter 8 PIN[7:0] 8:1 PARALLEL TO SERIAL PICLK TIMING GEN LLEB SLPTIME MODE0 CLOCK SYNTHESIZER MODE1 RSTB CAP1 CAP2 TSTRST RLPTIME REFCLKP/N TTLREF Receiver SDTTL SDPECL 1:8 SERIAL TO PARALLEL ...

Page 4

S3033 S3033 TRANSCEIVER FUNCTIONAL DESCRIPTION TRANSMITTER OPERATION The S3033 transceiver chip performs the serializing stage in the processing of a transmit SONET STS-3 or STS-12 bit serial data stream. It converts the 8-bit parallel 19.44 or 77.76 Mbyte/sec data stream ...

Page 5

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER RECEIVER OPERATION The S3033 transceiver chip provides the first stage of the digital processing of a receive SONET STS-3 or STS-12 bit-serial stream. It converts the bit-serial 155.52 or 622.08 Mbps data stream into a 19.44 or ...

Page 6

S3033 OTHER OPERATING MODES Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the re- ceiver at the serial data rate can be set up for diagnostic purposes. The differential serial output ...

Page 7

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER Table 4. Transmitter Pin Assignment and Descriptions ...

Page 8

S3033 Table 5. Receiver Pin Assignment and Descriptions ...

Page 9

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER Table 6. Common Pin Assignment and Descriptions ...

Page 10

S3033 Table 6. Common Pin Assignment and Descriptions (Continued ...

Page 11

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER Figure 5. 64 PQFP/TEP Package TOP VIEW Table 7. Thermal Management April 7, 2000 / Revision D ...

Page 12

S3033 Figure 6. Pinout Assignments TXCOREGND TXCOREVCC TTLREF REFCLKN REFCLKP AVCC1 AGND1 CAP2 CAP1 AGND0 AVCC0 TSTRST LLEB RLPTIME NC TXOUTVCC 12 SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER S3033 PQFP/TEP 9 TOP VIEW 10 ...

Page 13

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER Table 8. Performance Specifications ...

Page 14

S3033 Table 9. Absolute Maximum Ratings ...

Page 15

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER Table 11. LVTTL Input/Output DC Characteristics ...

Page 16

S3033 Table 13. Transmitter AC Timing Characteristics ...

Page 17

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER Table 14. Receiver AC Timing Characteristics ...

Page 18

S3033 RECEIVER FRAMING Figure 11 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF and remains enabled while OOF is High. Both boundaries ...

Page 19

SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER S3033 WITH DATA CLOCK SYNCHRONOUS TO REFERENCE CLOCK In some applications it is necessary to "forward clock" the data in a SONET/SDH system. In this ap- plication the reference clock from which the high speed serial clock ...

Page 20

S3033 Ordering Information – Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 ...

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