S3056 AMCC (Applied Micro Circuits Corp), S3056 Datasheet

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S3056

Manufacturer Part Number
S3056
Description
Multi-rate Sonet/sdh Clock Recovery Unit
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

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S3056TT
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FEATURES
Figure 1. System Block Diagram
October 31, 2000 / Revision J
DEVICE
SPECIFICATION
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
BiCMOS PECL CLOCK GENERATOR
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
SiGe BiCMOS technology
Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for:
OC-48 (2488.32 Mbps),
Fibre Channel (2125 Mbps),
OC-24 (1244.16 Mbps),
Gigabit Ethernet (1250 Mbps),
Fibre Channel (1062.5 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps) NRZ data
Selectable reference frequencies
19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
Gigabit Ethernet frequencies)
Lock detect—monitors frequency of
incoming data
Low-jitter serial interface
+3.3 V supply
Compact 48 pin TQFP TEP package
Typical power 620 mW
16
16
S3057
S3056
OTX
ORX
ORX
GENERAL DESCRIPTION
The function of the S3056 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3056 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3056 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ sig-
nal and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3056 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
OTX
S3056
S3057
16
16
S3056
S3056
®
1

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S3056 Summary of contents

Page 1

... S3057 16 October 31, 2000 / Revision J GENERAL DESCRIPTION The function of the S3056 clock recovery unit is to derive high speed timing signals for SONET/SDH- based equipment. The S3056 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figure 1 shows a typical network application. The S3056 receives an OC-48, OC-24, OC-12, OC-3, Fibre Channel or Gigabit Ethernet scrambled NRZ sig- nal and recovers the clock from the data ...

Page 2

... S3056 S3056 OVERVIEW The S3056 supports clock recovery for the OC-48, Fibre Channel (2125 Mbps), OC-24, Gigabit Ethernet, Fibre Channel (1062.5 Mbps), OC-12 or OC-3 data rate. Differential serial data is input to the chip at the specified rate, and clock recovery is per- formed on the incoming data stream. An external os- ...

Page 3

... SONET equipment by the Bellcore TA-NWT-000253 standard, shown in Figure 3. Lock Detect The S3056 contains a lock detect circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions ...

Page 4

... S3056 SONET JITTER CHARACTERISTICS Performance The S3056 PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, De- cember 1995 and ITU-T Recommendations: G.958 document, when used as specified. Input Jitter Tolerance Input jitter tolerance is defined as the peak to ...

Page 5

... MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT FIBRE CHANNEL JITTER CHARACTERISTICS Performance The S3056 PLL complies with the jitter specifications proposed for Fibre Channel equipment defined by the fibre channel methodology for Jitter specification. Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 dB opti- cal/electrical power penalty ...

Page 6

... S3056 Table 5. Pin Assignment and Descriptions ...

Page 7

... S3056 . n 7 ...

Page 8

... S3056 Figure 6. S3056 48 Pin TQFP/TEP Pinout VCC SERDATIN SERDATIP GND VCC REFCLKP REFCLKN GND VCC LOCKDET GND GND 8 MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT S3056 6 48 Pin TQFP/TEP 7 8 Top View GND 35 VCC 34 SERCLKOP 33 SERCLKON 32 VCC 31 GND 30 GND ...

Page 9

... MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Figure 7. 48 Pin TQFP/TEP Package TOP VIEW Table 6. Thermal Management October 31, 2000 / Revision S3056 ˚ ...

Page 10

... S3056 Table 7. Performance Specifications ...

Page 11

... < f < < f < S3056 11 ...

Page 12

... Electrostatic Discharge (ESD) Ratings The S3056 is rated to the following voltages based on the human body model: 1. All pins are rated 100 Volts except pin # 40 (CAP1) and pin # 39 (CAP2). Adherence to standards for ESD protection should be taken during the handling of the devices to ensure that the devices are not damaged. The standards to be used are defined in ANSI standard ANSI/ESD S20.20-1999, " ...

Page 13

... µ Max. = 3.465 V. TTL S3056 ...

Page 14

... S3056 Table 15. Single Ended LVPECL Input DC Characteristics ...

Page 15

... MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Figure 10. +5V Differential PECL Driver to S3056 Differential CML Input AC Coupled Termination +5 V Figure 11. S3056 Differential CML Output to S3057/S3067 Terminations +3.3 V S3056 SERDATOP/N SERCLKOP/N Figure 12. +5V Differential PECL Driver to S3056 Reference Clock Input AC Coupled Termination +5 V 155 MHz ...

Page 16

... S3056 Figure 13. +3V Differential LVPECL Driver to S3056 Reference Clock Input DC Coupled Termination +3 V 155 MHz OSCILLATOR/ 155MCK from S3057 Figure 14. Loop Filter Capacitor Connections 16 MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Vcc -0.5 V Zo=50 150 100 150 Zo=50 Vcc -0.5 V S3056 REFCLKP/N 56 CAP1 10 F CAP2 56 S3056 +3.3 V October 31, 2000 / Revision J ...

Page 17

... AMCC is a registered trademark of Applied Micro Circuits Corporation. October 31, 2000 / Revision XXXX X XX Prefix Device Package http://www.amcc.com Copyright ® 2000 Applied Micro Circuits Corporation S3056 – ...

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