S3091 AMCC (Applied Micro Circuits Corp), S3091 Datasheet
S3091
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S3091 Summary of contents
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... SONET-based ATM applications. Figure 1 shows a typical network application. On-chip clock synthesis PLL components are con- tained in the S3091 MUX chip, allowing the use of a slower external transmit clock reference. The chip can be used with a 155.52 or 622.08 MHz reference clock (or equivalent FEC or DW rate), in support of existing system clocking schemes ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter FEATURES .............................................................................................................................................................. 1 APPLICATIONS ...................................................................................................................................................... 1 GENERAL DESCRIPTION ...................................................................................................................................... 1 CONTENTS ............................................................................................................................................................. 2 LIST OF FIGURES .................................................................................................................................................. 3 LIST OF TABLES .................................................................................................................................................... 3 SONET OVERVIEW ................................................................................................................................................ 4 Data Rates and Signal Hierarchy ...................................................................................................................... 4 Frame and Byte Boundary Detection ................................................................................................................ 4 S3091 OVERVIEW .................................................................................................................................................. 6 S3091 ARCHITECTURE/FUNCTIONAL DESIGN .................................................................................................. 7 MUX OPERATION ............................................................................................................................................ 7 Clock Divider and Phase Detector ..................................................................................................................... 7 Timing Generator ............................................................................................................................................... 7 Parallel-to-Serial Converter ............................................................................................................................... 8 FIFO ...
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... Figure 12. S3091 LVDS Driver to LVDS Input, Reference Only ............................................................................ 21 Figure 13. LVDS Driver to S3091 LVDS Input Direct Coupled Termination, Reference Only ............................... 21 Figure 14. LVDS Driver to S3091 LVDS Input AC Coupled Termination, Reference Only .................................... 22 Figure 15. External Loop Filter ............................................................................................................................... 22 Figure 16. S3091 622.08 MHz REFCLK Phase Noise Limit .................................................................................. 23 Figure 17 ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter SONET OVERVIEW Synchronous Optical Network (SONET standard for connecting one fiber system to another at the opti- cal level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber intercon- nect betwe en tel ephone net works of diff erent countries ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 3. STS-192 Frame Format 192 A1 Bytes Transport Overhead 576 Columns 576 5,184 bytes A2 A2 192 A2 Bytes Synchronous Payload Envelope 16,704 Columns 16,704 150,336 bytes 125 µsec Revision A – February 22, 2002 DEVICE SPECIFICATION ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter S3091 OVERVIEW The S3091 transmitter implements SONET/SDH seri- alization and transmission functions. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip includes par- allel-to-serial conversion and system timing ...
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... Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3091 device. In the parallel-to-serial conversion process, the incom- ing data is passed from the PICLK clock timing domain to the internally generated byte clock timing domain using an internal FIFO ...
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... PHERR will go inactive when the realignment is complete. (See Figure 9, Phase Adjust Timing.) Power Sequencing In order to avoid latchup required that the -5.2 V power be applied to the S3091 for a minimum before 3.3 V power is applied. Table 4. Clock Select CLKSEL PICLK Frequency 0 622 ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Table 6. Input Pin Assignment and Descriptions Pin Name Level I/O PINP0 LVDS I PINN0 PINP1 PINN1 PINP2 PINN2 PINP3 PINN3 PINP4 PINN4 PINP5 PINN5 PINP6 PINN6 PINP7 PINN7 PINP8 PINN8 PINP9 PINN9 PINP10 PINN10 PINP11 PINN11 PINP12 PINN12 ...
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... See Characterization Report for S B11 Parallel Clock. A 622.08 MHz clock normally used to coordi- A11 nate transfers between upstream logic and the S3091 device. B10 155.52 MHz Clock Output. 155.52 MHz clock output from the B9 clock synthesizer. The output should be connected to the reference clock input of the external clock recovery function (such as the S3092) ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Table 8. Common Pin Assignment and Descriptions Pin Name Level AVEE -5.2 V VEE_FILTER -5.2 V VEE_VCO -5.2 V DGND GND = 0 V AGND GND = 0 V THERMALGND GND = 0 V VCCLVDS +3.3 V VCCLVTTL +3.3 V Note: All digital, analog, and thermal grounds are connected together on the package. Pin # ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 5. S3091 Pinout AGND AGND VEE FILTER AGND B REFCLKP AGND AGND CAP1 C REFCLKN AGND AGND CAP2 VEE D AGND REFCLK E AGND AVEE F AGND AGND G TSDP H AGND AGND J TSDN K AGND AGND L AGND AVEE M AGND REFSEL VCCLVDS ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 6. S3091 148-Pin CBGA Package Table 9. Thermal Management Package Max Power Device S3091 Note: See application note for simulation results, thermal management suggestions and thermal profile for attachment. (70°C Ambient) 2.68 W 20.5°C/W Revision A – February 22, 2002 DEVICE SPECIFICATION Θ ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Table 10. Performance Specifications Parameter Nominal VCOCLK Center Fre- quency Data Output Jitter STS-192 with 622.08 MHz REFCLK. Data Output Jitter STS-192 with155.52 MHz REFCLK. TSDP/N Output Return Loss (S 22 Reference Clock Frequency Toler- ance Reference Clock Input Duty Cycle (622 ...
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... ECL Input Current per pin Electrostatic Discharge (ESD) Ratings The S3091 is rated to the following voltages based on the human body model: 1. All pins are rated at 100 Volts. Standards for ESD protection should be adhered to when handling the devices to ensure that they are not damaged. The standards to be used are defined in ANSI standard ANSI/ESD S20.20-1999, “ ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Table 13. LVTTL Input DC Characteristics Parameters Description V Input High Voltage IH V Input Low Voltage IL I Input High Current IH I Input Low Current IL Table 14. LVTTL Output DC Characteristics Parameters Description V Output High Voltage OH V Output Low Voltage OL Table 15. Differential CML Output DC Characteristics ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Table 17. Internally Biased LVDS Input Characteristics Symbol Description V Input High Voltage IH V Input Low Voltage IL V Input Voltage Differential INDIFF V Input Single-ended Volt- INSINGLE age R Differential Input DIFF Resistance Table 18. LVDS Output DC Characteristics Symbol Description V Output High Voltage ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Table 19. AC Transmitter Timing Characteristics (PICLKP/N = 622.08 MHz) Symbol PICLKP/N Duty Cycle = tD tS PINP/N[15:0] Set-up Time w.r.t. rising edge of PICLKP (622.08 MHz PICLK) PIN tH PINP/N[15:0] Hold Time w.r.t. rising edge of PICLKP (622.08 MHz PICLK) PIN PCLKP/N Duty Cycle ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Table 20. AC Transmitter Timing Characteristics (PICLKP/N = 311.04 MHz) Symbol PICLKP/N Duty Cycle = LVDS output rise and fall times (20 PINP/N[15:0] setup time w.r.t. next edge of PICLKP (311.04 MHz PICLK) PIN tH PINP/N[15:0] hold time w.r.t. next edge of PICLKP (311.04 MHz PICLK) ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 9. Phase Adjust Timing PHERR PHINIT PCLK PICLK TRANSFER CLK (Internal) Note: The byte clock = 622.08 MHz to 669.33 MHz. Figure 10. Differential Voltage Measurement V(+) WRT GND V(-) WRT GND 0 V V(+) WRT V(-) 0 V Note: WRT = with respect to Note: V(+) - V(-) is the algebraic difference of the input signals. ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 11. CML Output to -5.2 V ECL Input DC Coupled Termination, Reference Only -5.2 V Figure 12. S3091 LVDS Driver to LVDS Input, Reference Only +3.3 V LVDS Output Figure 13. LVDS Driver to S3091 LVDS Input Direct Coupled Termination, Reference Only +3.3 V LVDS Output 0 V Zo=50 Ω Zo=50 Ω S3091 TSDP/N Zo=50 Ω ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 14. LVDS Driver to S3091 LVDS Input AC Coupled Termination, Reference Only +3.3 V LVDS Output Figure 15. External Loop Filter 22 Zo=50 Ω 0.1µF Zo=50 Ω 0.1µ CAP2 CAP1 Revision A – February 22, 2002 DEVICE SPECIFICATION DC Bias +3.3 V 100 Ω Bias ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 16. S3091 622.08 MHz REFCLK Phase Noise Limit -55 -65 -75 -85 -95 -105 -115 -125 -135 -145 100 1,000 10,000 Note: Using an oscillator with one of the phase noise spectrums shown above, will yield the respective jitter generation numbers associ- ated with each phase noise plot ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Figure 17. S3091 155.52 MHz REFCLK Phase Noise Limit -60 -80 -100 -120 -140 -160 100 1,000 Note: Using an oscillator with either phase noise spectrum shown above, will yield similar jitter generation as the integrated phase noise under each mask is similar. ...
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... S3091 – SONET/SDH/ATM OC-192 16:1 Transmitter Prefix S - Integrated Circuit Prefix Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current ...