GS1559 Gennum Corp., GS1559 Datasheet
GS1559
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GS1559 Summary of contents
Page 1
... HD/SD operational requirements. The GS1559 also includes a range of data processing functions such as error detection and correction, automatic standards detection, and EDH support. The device can also detect and extract SMPTE 352M payload identifier packets and independently identify the received video standard ...
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... Word alignment and flywheel S->P K28.5 sync detect, DVB-ASI word alignment and 8b/10b decode HOST Interface / JTAG Reset GS1559 Functional Block Diagram 30572 - 4 July 2005 GS1559 Data Sheet CRC correct CRC check Line mumber Line mumber correct check TRS correct TRS check ...
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... Serial-To-Parallel Conversion .......................................................................30 4.6 Modes Of Operation......................................................................................31 4.6.1 Lock Detect.........................................................................................31 4.6.2 Master Mode.......................................................................................32 4.6.3 Slave Mode.........................................................................................32 4.7 SMPTE Functionality ....................................................................................34 4.7.1 SMPTE Descrambling and Word Alignment .......................................34 4.7.2 Internal Flywheel.................................................................................34 4.7.3 Switch Line Lock Handling..................................................................35 4.7.4 HVF Timing Signal Generation ...........................................................39 4.8 DVB-ASI Functionality ..................................................................................41 4.8.1 DVB-ASI 8b/10b Decoding and Word Alignment................................41 30572 - 4 July 2005 GS1559 Data Sheet ...
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... Device Reset...............................................................................................68 5. Application Reference Design ................................................................................69 5.1 Typical Application Circuit (Part A) ...............................................................69 5.2 Typical Application Circuit (Part B) ...............................................................70 6. References & Relevant Standards .........................................................................71 7. Package & Ordering Information............................................................................72 7.1 Package Dimensions ....................................................................................72 7.2 Packaging Data.............................................................................................73 7.3 Ordering Information .....................................................................................73 8. Revision History .....................................................................................................74 30572 - 4 July 2005 GS1559 Data Sheet ...
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... NC 10bit IOPROC DDI2 _EN/DIS CS_ NC H TERM2 DDI2 TMS J NC CD2 RSET CD_VDD SDO SD0 30572 - 4 July 2005 GS1559 Data Sheet VCO NC IO_VDD PCLK DOUT18 NC FW_EN/ IO_GND NC DOUT16 /DIS MASTER/ NC DOUT14 RC_BYP YANC SLAVE DVB_ASI LOCKED NC CANC ...
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... Signal levels are LVCMOS/LVTTL compatible. HD 20-bit mode HD 10-bit mode SD 20-bit mode SD 10-bit mode – Power Power supply connection for digital I/O buffers. Connect to +3.3V DC digital. 30572 - 4 July 2005 GS1559 Data Sheet PCLK = 74.25MHz or 74.25/1.001MHz PCLK = 148.5MHz or 148.5/1.001MHz PCLK = 13.5MHz PCLK = 27MHz ...
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... Ground connection for the charge pump. Connect to analog GND. Analog Input Control voltage to set the loop bandwidth of the integrated reclocker. Normally connected to VCO_GND through 40kΩ. 30572 - 4 July 2005 GS1559 Data Sheet Luma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW ...
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... In this mode, the GS1559 will automatically detect, reclock, deserialize and process SD SMPTE, HD SMPTE, or DVB-ASI input data. When set LOW, the GS1559 is set to operate in slave mode where DVB_ASI, SD/HD, RC_BYP and SMPTE_BYPASS become control signal input pins. In this mode, the application layer must set these external device pins for the correct reception of either SMPTE or DVB-ASI data ...
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... PCLK Signal levels are LVCMOS / LVTTL compatible. The LOCKED signal will be HIGH whenever the device has correctly received and locked to SMPTE compliant data in SMPTE mode or DVB-ASI compliant data in DVB-ASI mode. It will be LOW otherwise. 30572 - 4 July 2005 GS1559 Data Sheet ...
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... When LOW, the serial digital input signal received at the DDI1 and DDI1 pins is considered valid. When HIGH, the associated serial digital input signal is considered to be invalid. In this case, the LOCKED signal is set LOW and all parallel outputs are muted. 30572 - 4 July 2005 GS1559 Data Sheet ...
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... SD 10-bit mode SD/HD = HIGH 20bit/10bit = LOW Analog Input Differential input pair for serial digital input 2. 30572 - 4 July 2005 GS1559 Data Sheet Chroma data output in SMPTE mode SMPTE_BYPASS =HIGH DVB_ASI = LOW Data output in Data-Through mode SMPTE_BYPASS = LOW DVB_ASI = LOW Forced LOW in all modes. ...
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... SD/HD data rate change. JTAG Test Mode (JTAG/HOST = HIGH) When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. 30572 - 4 July 2005 GS1559 Data Sheet ...
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... The DATA_ERROR signal will be HIGH when the received data stream has been detected without error. NOTE possible to program which error conditions are monitored by the device by setting appropriate bits of the ERROR_MASK register HIGH. All error conditions are detected by default. 30572 - 4 July 2005 GS1559 Data Sheet ...
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... The V signal will be LOW for all lines outside of the vertical blanking interval. Analog Input Used to set the serial digital loop-through output signal amplitude. Connect to CD_VDD through 281Ω +/- 1% for 800mV 30572 - 4 July 2005 GS1559 Data Sheet ) single-ended output swing. p ...
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... Used to indicate the ODD / EVEN field of the video signal. The F signal will be HIGH for the entire period of field 2 as indicated by the F bit in the received TRS signals. The F signal will be LOW for all lines in field 1 and for all lines in progressive scan systems. 30572 - 4 July 2005 GS1559 Data Sheet ...
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... Min – 0 – 1.71 – 3.13 – 3.13 – 1.71 – 1.71 – 1.71 – 2.25 SDO – Enabled – – 30572 - 4 July 2005 GS1559 Data Sheet Value/Units -0.3V to +2.1V -0.3V to +4.6V -2. 5.25V -20°C < T < 85°C A -40°C < T < 125°C STG 1kV Typ Max Units Test Level – 70 °C 3 1.8 1. ...
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... RSET=281Ω, SD and HD NOTES 1. All DC and AC electrical parameters within specification. 2. Input common mode is set by internal biasing resistors. 3. Set by the value of the RSET resistor. 4. Sum of all 1.8V supplies. 5. Sum of all 3.3V supplies. 30572 - 4 July 2005 GS1559 Data Sheet Typ Max Units Test Level – 550 mW 3 – ...
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... RSET = 281Ω 650 Load = 75Ω HD signal – SD signal 400 HD signal – SD signal 400 30572 - 4 July 2005 GS1559 Data Sheet Typ Max Units Level – – UI – 468 us – 260 us – 135 us – 340 us – ...
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... NOTES 1. 6MHz sinewave modulation 1080i 525i 3. Serial Digital Output Reclocked ( 4. See 30572 - 4 July 2005 GS1559 Data Sheet Typ Max Units Test Level 90 125 ps 270 350 ps – 148.5 MHz – – ...
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... Solder Reflow Profiles The GS1559 is available Pb-free package recommended that the Pb package be soldered with Pb paste using the Standard Eutectic profile shown in Figure 2-1, and the Pb-free package be soldered with Pb-free paste using the reflow profile shown in Figure 2-2. NOTE possible to solder a Pb-free package with Pb paste using a Standard ...
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... Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown. DDI VDD 50 45K TERM 150K 50 DDI Figure 3-1: Serial Digital Input VCO VDD 25 1. VCO Figure 3-2: VCO Input 7.2K 865mV Figure 3-3: PLL Loop Bandwidth Control 30572 - 4 July 2005 GS1559 Data Sheet LB_CONT ...
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... Figure 3-4: Serial Digital Output LF CP_CAP 300 Figure 3-5: VCO Control Output & PLL Lock Time Capacitor 30572 - 4 July 2005 GS1559 Data Sheet SDO SDO ...
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... Detailed Description 4.1 Functional Overview 4.2 Serial Digital Input The GS1559 is a multi-rate reclocking deserializer with an integrated serial digital loop-through output. When used in conjunction with the multi-rate GS1574 Adaptive Cable Equalizer and the external GO1525 Voltage Controlled Oscillator, a receive solution at 1.485Gb/s, 1.485/1.001Gb/s or 270Mb/s is realized. ...
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... A 2x1 input multiplexer is provided to allow the application layer to select between the two serial digital input streams using a single external pin. When IP_SEL is set HIGH, serial digital input 1 (DDI1 / DDI1) is selected as the input to the GS1559's reclocker stage. When IP_SEL is set LOW, serial digital input 2 (DDI2 / DDI2) is selected ...
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... The internal regulator uses +3.3V DC supplied via the CP_VDD / CP_GND pins to provide +2. the VCO_VCC / VCO_GND pins. The control voltage to the VCO is output from the GS1559 on the LF pin and requires 4.7kΩ pull-up and pull-down resistors to ensure correct operation. The GO1525 produces a 1.485GHz reference signal for the reclocker, input on the VCO pin of the GS1559 ...
Page 29
... When operating in master mode, the device will assert the RC_BYP pin HIGH only when it has successfully locked to a SMPTE or DVB-ASI input data stream, (see Lock Detect on page 31). In this case, the serial digital loop-through output will be a reclocked version of the input. 30572 - 4 July 2005 GS1559 Data Sheet 550 600 650 700 750 p-p Figure 4-1 ...
Page 30
... Serial Digital Output Mute 4.5 Serial-To-Parallel Conversion The GS1559 will automatically mute the serial digital loop-through output in both master and slave modes when the internal carrier_detect signal indicates an invalid serial input. The loop-through output will also be muted in slave mode when SDO/SDO is selected as reclocked, (RC_BYP = HIGH), but the lock detect block has failed to lock to the data stream, (LOCKED = LOW) ...
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... Modes Of Operation 4.6.1 Lock Detect The GS1559 has two basic modes of operation which determine how the lock detect block controls the integrated reclocker. Master mode is enabled when the application layer sets the MASTER/SLAVE pin HIGH, and slave mode is enabled when MASTER/SLAVE is set LOW. ...
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... The combined setting of these four pins will indicate whether the device has locked to valid SMPTE or DVB-ASI data rates. combinations. The GS1559 is said slave mode when the MASTER/SLAVE input signal is set LOW. In this case, the four device pins listed in become input control signals. ...
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... Table 4-3: Slave Mode Input Control Signals FORMAT SMPTE_BYPASS HD SMPTE HIGH SD SMPTE HIGH DVB-ASI LOW NOT SMPTE OR LOW DVB-ASI* *NOTE: See Data Through Mode on page 42 30572 - 4 July 2005 GS1559 Data Sheet PIN SETTINGS DVB_ASI SD/HD LOW LOW LOW HIGH HIGH HIGH LOW HIGH OR LOW PIN SETTINGS DVB_ASI SD/HD ...
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... SMPTE Functionality 4.7.1 SMPTE Descrambling and Word Alignment 4.7.2 Internal Flywheel The GS1559 is said SMPTE mode once the device has detected SMPTE TRS sync words and locked to the input data stream as described in on page 31. The device will remain in SMPTE mode until such time that SMPTE TRS sync words fail to be detected ...
Page 35
... To account for the horizontal disturbance caused by a synchronous switch necessary to re-synchronize the flywheel immediately after the switch has taken place. Rapid re-synchronization of the GS1559 to the new video standard can be achieved by controlling the flywheel using the FW_EN/DIS pin. At every PCLK cycle the device samples the FW_EN/DIS pin. When a logic LOW to HIGH transition at this pin is detected anywhere within the active line, the flywheel will re-synchronize immediately to the next TRS word ...
Page 36
... The GS1559 also implements automatic switch line lock handling. By utilizing the synchronous switch points defined by SMPTE RP168 for all major video standards with the automatic video standards detect function, the device automatically re-synchronizes the flywheel at the switch point ...
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... Table 4-4 may not correspond directly to the digital line counts. NOTE 2: Unless indicated by SMPTE 352M payload identifier packets, the GS1559 will not distinguish between 50/60 frames PsF and 25/30 frames interlaced for the 1125 line video systems; 24 PsF will be identified. Sampling Signal Standard ...
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... BT.1358 4:2:0 BT.1358 4:2:0 BT.1358 4:2:2 BT.601 4:2:2 BT.601 4:4:4:4 BT.799 4:4:4:4 BT.799 4:4:4:4 BT.799 4:4:4:4 BT.799 4:2:2 BT.601 4:2:2 BT.601 30572 - 4 July 2005 GS1559 Data Sheet Parallel Serial Interface Interface 349M 292M 267M 259M 349M 292M 347M 344M RP174 344M RP175 RP175 349M 292M 125M 259M 349M 292M 347M 344M ...
Page 39
... HVF Timing Signal Generation The GS1559 extracts critical timing parameters from either the received TRS signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator (FW_EN/DIS = HIGH). Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F) timing are all extracted and presented to the application layer via the H:V:F status output pins ...
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... H;V:F TIMING AT SAV - HD 10-BIT OUTPUT MODE 000 3FF XYZ 000 (eav) H:V:F TIMING - SD 20-BIT OUTPUT MODE XYZ 000 (eav) H:V:F TIMING - SD 10-BIT OUTPUT MODE July 2005 GS1559 Data Sheet XYZ 3FF 000 000 (sav) XYZ 3FF 000 000 (sav) XYZ XYZ 000 ...
Page 41
... DVB-ASI Functionality 4.8.1 DVB-ASI 8b/10b Decoding and Word Alignment 4.8.2 Status Signal Outputs The GS1559 is said DVB-ASI mode once the device has detected 32 consecutive DVB-ASI words without a single word or disparity error being generated. The device will remain in DVB-ASI mode until 32 consecutive DVB-ASI word or disparity errors are detected, or until SMPTE TRS ID words have been detected ...
Page 42
... FIFO Load Pulse GS1559 Figure 4-4: DVB-ASI FIFO Implementation Using The GS1559 The GS1559 may be configured by the application layer to operate as a simple serial-to-parallel converter. In this mode, the device presents data to the output data bus without performing any decoding, descrambling or word-alignment. Data through mode is enabled only when the MASTER/SLAVE, SMPTE_BYPASS, and DVB_ASI input pins are set LOW ...
Page 43
... FIFO LOAD PULSE - SD 10BIT OUTPUT MODE Figure 4-5: FIFO_LD Pulse Timing The GS1559 will detect all types of ancillary data in either the vertical or horizontal blanking spaces and indicate via the status signal output pins YANC and CANC the position of ancillary data in the output data stream. These status signal outputs are synchronous with PCLK and can be used as clock enables to external logic write enables to an external FIFO or other memory device ...
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... DID DBN 3FF ANC DATA ANC DATA ANC DATA DETECTION - SD 20BIT OUTPUT MODE DID DBN 3FF ANC DATA DETECTION - SD 10BIT OUTPUT MODE July 2005 GS1559 Data Sheet Parallel Data Figure 4-6. BLANK CSUM ANC DATA ANC DATA ANC DATA CSUM ANC DATA ...
Page 45
... SDID is set to zero, the device will detect all ancillary data types matching the DID value, regardless of the SDID. In the case where all five DID and SDID values are set to zero, the GS1559 will detect all ancillary data types. This is the default setting after device reset. ...
Page 46
... Should be set to zero if no SDID is present in the ancillary data packet to be detected. The GS1559 can receive and detect the presence of the SMPTE 352M payload identifier ancillary data packet. This four word payload identifier packet may be used to indicate the transport mechanism, frame rate and line scanning / sampling structure ...
Page 47
... Byte 1 Payload Identification Packets are detected in the data stream. The GS1559 can independently detect the input video standard and data format by using the timing parameters extracted from the received TRS ID words. This information is presented to the host interface via the VIDEO_STANDARD register (Table 4-7) ...
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... EM 198 1280x720/30 (1:1) 2008 1280x720/30 (1: 408 1280x720/50 (1:1) 688 1280x720/50 (1: 240 1280x720/25 (1:1) 2668 30572 - 4 July 2005 GS1559 Data Sheet R/W Table 4-9). Table 4-10). Description R/W Not Used. Words Per Active Line. R Not Used. Words Per Total Line. R Not Used. Total Lines Per Frame. ...
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... July 2005 GS1559 Data Sheet Length of Total SMPTE352M Active Video Samples 3456 3960 1280 4125 3600 4125 1920 2200 1920 2200 ...
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... Other SDTI variable block size 6h SDI 7h DVB-ASI 8h TDM data Reserved Fh Unknown data format 30572 - 4 July 2005 GS1559 Data Sheet '. h Table 4-10. ' after device reset. These bits will h Data Through Mode on page Applicable Standards SMPTE 321M SMPTE 321M SMPTE 322M SMPTE 326M – ...
Page 51
... Error Detection and Indication The GS1559 contains a number of error detection functions to enhance operation of the device when operating in SMPTE mode. These functions, (except lock error detection), will not be available in either DVB-ASI or Data-Through operating modes. See DVB-ASI Functionality on page 41 page 42. The device maintains an error status register at address 001 ...
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... FW_EN/DIS must be set HIGH. End of Active Video Error Flag. Set HIGH when TRS errors are detected in either 8-bit or 10-bit TRS words mode only Y channel TRS codes will be checked. FW_EN/DIS must be set HIGH. 30572 - 4 July 2005 GS1559 Data Sheet R/W Default – – ...
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... End of Active Video Error Flag Mask bit mismatch between the received SMPTE 352M packets and the calculated video standard occurs, the GS1559 will indicate a video standard error by setting the VD_STD_ERR bit of the ERROR_STATUS register HIGH. The GS1559 calculates Full Field (FF) and Active Picture (AP) CRC words according to SMPTE RP165 in support of Error Detection and Handling packets in SD signals ...
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... Field 1 Active Picture end line data used to set EDH calculation range outside of SMPTE RP 165 values. Not Used. Field 1 Active Picture end line data used to set EDH calculation range outside of SMPTE RP 165 values. 30572 - 4 July 2005 GS1559 Data Sheet R/W Default – – R/W 0 – – ...
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... Field 1 Full Field end line data used to set EDH calculation range outside of SMPTE RP 165 values. The LOCKED pin of the GS1559 indicates the lock status of the reclocker and lock detect blocks of the device. Only when the LOCKED pin is asserted HIGH has the device correctly locked to the received data stream, (see The GS1559 will also indicate lock error to the host interface when LOCKED = LOW by setting the LOCK_ERR bit in the ERROR_STATUS register HIGH ...
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... HD Line Number Error Detection 4.10.5.7 TRS Error Detection The GS1559 will calculate line based CRC words for HD video signals for both the Y and C data channels. These calculated CRC values are compared with the received CRC values and any mismatch is flagged in the YCRC_ERR and/or CCRC_ERR bits of the ERROR_STATUS register ...
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... LNUM_INS 0 TRS_INS In addition to signal error detection and indication, the GS1559 may also correct certain types of errors by inserting corrected code words, checksums and CRC values into the data stream. These features are only available in SMPTE mode and IOPROC_EN/ must be set HIGH. Individual correction features may be enabled ...
Page 58
... This feature is only available in HD mode and is enabled by setting the CRC_INS bit of the IOPROC_DISABLE register LOW mode, the GS1559 will calculate and insert line numbers into the Y and C channels of the output data stream. Line number generation is in accordance with the relevant HD video standard as ...
Page 59
... EDH flags may be set, and the source is replaced by one without EDH packets, the EDH_FLAG register will not be cleared. NOTE 3: The GS1559 will detect EDH flags, but will not update the flags if an EDH CRC error is detected. Gennum's GS1532 Multi-Rate Serializer allows the host to individually set EDH flags ...
Page 60
... Active Picture Unknown Error Status Flag. Active Picture Internal device error Detected Already Flag. Active Picture Internal device error Detected Here Flag. Active Picture Error Detected Already Flag. Active Picture Error Detected Here Flag. 30572 - 4 July 2005 GS1559 Data Sheet R/W Default – – ...
Page 61
... In master mode, however, the GS1559 sets these pins as output status signals. The parallel data outputs of the GS1559 are driven by high-impedance buffers which support both LVTTL and LVCMOS levels. These buffers use a separate power supply of +3.3V DC supplied via the IO_VDD and IO_GND pins. ...
Page 62
... SYNCOUT and WORDERR respectively. See page 41 for a description of these DVB-ASI specific output signals. DOUT[9:0] will be forced LOW when the GS1559 is operating in DVB-ASI mode. When operating in Data-Through mode, (see GS1559 presents data to the output data bus without performing any decoding, descrambling or word-alignment. ...
Page 63
... Data Through Mode on page forced to logic LOW if the device is set to operate in master mode but cannot identify SMPTE TRS ID or DVB-ASI sync words in the input data stream. The frequency of the PCLK output signal of the GS1559 is determined by the output data format. Table 4-16 below lists the possible output signal formats and their corresponding parallel clock rates ...
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... Figure 4-9. All read or write access to the GS1559 is initiated and terminated by the host processor. Each access always begins with a 16-bit command word on SDIN indicating the address of the register of interest. This is followed by a 16-bit data word on SDIN in write mode 16-bit data word on SDOUT in read mode. ...
Page 65
... When reading from the registers via the GSPI, the MSB of the data word will be available on SDOUT 12ns following the falling edge of the LSB of the command word, and thus may be read by the host on the very next rising edge of the clock. The remaining bits are clocked out by the GS1559 on the negative edges of SCLK. duty t ...
Page 66
... Configuration and Status Registers Table 4-17 summarizes the GS1559's internal status and configuration registers. All of these registers are available to the host via the GSPI and are all individually addressable. Where status registers contain less than the full 16 bits of information however, two or more registers may be combined at a single logical address. ...
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... JTAG When the JTAG/HOST input pin of the GS1559 is set HIGH, the host interface port will be configured for JTAG test operation. In this mode, pins and J6 become TMS, TCK, TDO, and TDI. In addition, the RESET_TRST pin will operate as the test reset pin. ...
Page 68
... CORE_VDD RESET_TRST The GS1559 has a recommended power supply sequence. To ensure correct power up, power the CORE_VDD pins before the IO_VDD pins. Device pins may also be driven prior to power up without causing damage. To ensure that all internal registers are cleared upon power-up, the application ...
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... Henrys, unless otherwise noted. EQ_VCC 10n 1 VEE_A EQ_GND 1u 2 SDI GS1574A 3 1u SDI 4 VEE_A 37R4 EQ_GND 470n 470n EQ_GND 30572 - 4 July 2005 GS1559 Data Sheet CD MUTE EQ_VCC 13 10n 12 + 4u7 VEE_D EQ_GND 11 SDO 10 + SDO 9 VEE_D 4u7 EQ_GND 8 MCLADJ BYPASS SDO SDO ...
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... " " 30572 - 4 July 2005 GS1559 Data Sheet ...
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... SMPTE 352M Video Payload Identification for Digital Television Interfaces SMPTE RP165 Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital Interfaces for Television SMPTE RP168 Definition of Vertical Interval Switching Point for Synchronous Video Switching 30572 - 4 July 2005 GS1559 Data Sheet ...
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... Package & Ordering Information 7.1 Package Dimensions 30572 - 4 July 2005 GS1559 Data Sheet ...
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... Junction to Case Thermal Resistance, θ Junction to Air Thermal Resistance, θ j-a Psi Pb-free Part Number Package GS1559-CBE2 100-ball BGA GS1559-CB 100-ball BGA 30572 - 4 July 2005 GS1559 Data Sheet Value 11mm x 11mm 100-ball LBGA JEDEC M0192 3 10.4°C/W j-c (at zero airflow) 37.1°C/W 0.4°C/W Yes Pb-free Package Temperature ...
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... The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. © Copyright 2004 Gennum Corporation. All rights reserved. Printed in Canada. 30572 - 4 July 2005 74 GS1559 Data Sheet ...