S2068 AMCC (Applied Micro Circuits Corp), S2068 Datasheet

S2068

Manufacturer Part Number

S2068

Description

Dual Gigabit Ethenet Transceiver

Manufacturer

AMCC (Applied Micro Circuits Corp)

Datasheet

1.S2068.pdf (24 pages)

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FEATURES

APPLICATIONS

Figure 1. Typical Dual Gigabit Ethernet Application

DEVICE

SPECIFICATION

DUAL GIGABIT ETHERNET TRANSCEIVER

June 20, 2000 / Revision B

• Functionally compliant with IEEE 802.3z Gigabit

• 1250 MHz (Gigabit Ethernet) operating rate

• Dual Transmitter incorporating phase-locked

• Dual Receiver PLL provides clock and data

• Internally series terminated TTL outputs

• Low-jitter serial PECL interface

• Local Loopback

• Interfaces with coax, twinax, or fiber optics

• Single +3.3V supply, 1.37W power dissipation

• Compact 21mm x 21mm 156 TBGA package

• Ethernet Backbones

• Multi-port Gigabit Ethernet Cards

• Switched networks

• Data broadcast environments

High-speed data communications

Ethernet Applications

– Half rate operation

loop (PLL) clock synthesis from low speed

reference

recovery

INTERFACE

ETHERNET

GIGABIT

DUAL

GE INTERFACE

S2068

GENERAL DESCRIPTION

The S2068 dual transmitter and receiver chip is de-

signed to provide two channels of high-speed serial

data transmission over fiber optic or copper interfaces

conforming to the requirements of the IEEE 802.3z

Gigabit Ethernet specification. The chip runs at

1250.0 Mbps serial data rate with an associated

10-bit parallel data word. The chip provides two sepa-

rate receive PLLs which can be operated

asyncronously at slightly different frequencies.

Each bi-directional channel provides parallel to serial

and serial-to-parallel conversion, clock generation

and recovery, and framing. The on-chip transmit PLL

synthesizes the high-speed clock from a low-speed

reference. The on-chip dual receive PLL is used for

clock recovery and data re-timing on the two inde-

pendent data inputs. The transmitter and receiver

each support differential PECL-compatible I/O for

copper or fiber optic component interfaces and pro-

vide excellent signal integrity. Local loopback mode

allows for system diagnostics. The chip requires a

3.3V power supply and dissipates 1.37 watts.

Figure 1 shows the use of the S2062 and S2068 in a

Gigabit Ethernet application. Figure 2 summarizes

the input/output signals of the device. Figures 3 and

4 show the transmit and receive block diagrams, re-

spectively.

(ASIC)

MAC

SERIAL BP DRIVER

S2062

TO SERIAL

BACKPLANE

S2068

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