GSM7980 Syntec Semiconductor, GSM7980 Datasheet - Page 17

• Manufacturer Part Number: GSM7980
• Description: Dot Matrix LCD Controller/Driver
• Manufacturer: Syntec Semiconductor

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l
Reset Function
Initializing by Internal Reset Circuit
An internal reset circuit automatically initializes the GSM7980 when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy
state
until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V.
1. Display clear
2. Function set:
LCD Controller / Driver
0
Write binary 8-bit data to DDRAM/CGRAM.
The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction
: DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC
direction to RAM.
After write operation, the address is automatically increased/decreased by 1, according to
the entry mode.
Read binary 8-bit data from DDRAM/CGRAM.
The selection of RAM is set by the previous address set instruction. If address set instruction of
RAM is not performed before this instruction, the data that read first is invalid, because the
direction of AC is not determined. If you read RAM data several times without RAM address set
instruction before read operation, you can get correct RAM data from the second, but the first
data would be incorrect, because there is no time margin to transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM
a
set instruction : it also transfer RAM data to output data register. After read operation address
counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM
read operation, display shift may not be executed correctly.
* In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In
this time, AC indicates the next address position, but you can read only the previous data by read
instruction.
DL = 1; 8-bit interface data
N = 0; 1-line display
Read Data from CGRAM or DDRAM
Syntek Semiconductor Co., Ltd.
Code
d
RS
1
RW DB7 DB6 DB5 DB4
1
D7
d
D6
D5
D4
17 / 17
DB3
D3
r
DB2
D2
DB1
D1
DB0
D0
e
ISSUE DATE :
s
GSM7980
s