ACS373D Intersil Corporation, ACS373D Datasheet

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ACS373D

Manufacturer Part Number
ACS373D
Description
Radiation Hardened Octal Transparent Latch, Three-state
Manufacturer
Intersil Corporation
Datasheet
April 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
• SEU LET Threshold >80 MEV-cm
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
• Input Current 1 A at VOL, VOH
Description
The Intersil ACS373MS is a radiation hardened octal transparent
latch with three-state outputs. The outputs are transparent to the
inputs when the latch enable (LE) is high. When the LE goes low,
the data is latched. When the Output Enable (OE) is high, the
outputs are in the high impedance state. The latch operation is
independent of the state of the output enable.
The ACS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Ordering Information
Truth Table
NOTE:
L = Low Voltage Level
H = High Voltage Level
I
h = High voltage level one set-up time prior to the high to low latch enable transition
ACS373DMSR
ACS373KMSR
ACS373D/Sample
ACS373K/Sample
ACS373HMSR
<1 x 10
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
= Low voltage level one set-up time prior to the high to low latch enable transition
OE
PART NUMBER
H
L
L
L
L
-10
Errors/Bit-Day (Typ)
11
LE
H
H
X
L
L
RAD (Si)/s, 20ns Pulse
TEMPERATURE RANGE
X = Don’t Care
Z = High Impedance State
o
2
C to +125
/mg
-55
-55
o
o
C to +125
C to +125
D
H
L
h
X
I
+25
+25
+25
o
o
o
o
C
C
C
C
o
o
C
C
Q
H
H
Z
L
L
1
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
Octal Transparent Latch, Three-State
Pinouts
SCREENING LEVEL
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C
GND
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C
OE
Q0
Q1
Q2
Q3
D0
D1
D2
D3
ACS373MS
Functional Diagram
(11)
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
COMMON
CONTROLS
LE
OE
(1)
D
20 LEAD CERAMIC DUAL-IN-LINE
20 LEAD CERAMIC FLATPACK
GND
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
10
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
TOP VIEW
TOP VIEW
LATCH
D
Radiation Hardened
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
LE
Q
Spec Number
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
PACKAGE
File Number
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
(2, 5, 6, 9, 12,
OE
15, 16, 19)
Q
518799
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
3999

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