ACS8595 Semtech Corporation, ACS8595 Datasheet - Page 6

• Manufacturer Part Number: ACS8595
• Description: Line Card Protection Switch for Sonet/sdh Advancedtca Systems
• Manufacturer: Semtech Corporation

Either the software or an internal state machine controls
the operation of DPLL1. The state machine for DPLL2 is
very simple and cannot be manually/externally controlled.
One additional feature of DPLL2 is the ability to measure
a phase difference between two inputs.
DPLL1 always produces an output at 77.76 MHz to feed
the APLL, regardless of the frequency selected at the
output pins or the locking frequency (frequency at the
input of the Phase and Frequency Detector — PFD).
DPLL2 can be operated at a number of frequencies. This
is to enable the generation of extra output frequencies,
which cannot be easily related to 77.76 MHz. If DPLL2 is
enabled, it locks to the 8 kHz from DPLL1. This is because
all of the frequencies of operation of DPLL2 can be
divided to 8 kHz and this will ensure synchronization of
frequencies, from 8 kHz upwards, within the two DPLLs.
APLLs
There are three APLLs. APLL1 and APLL2 provide a lower
final output jitter reducing the 4.9 ns p-p jitter from the
digital down to 500 ps p-p and 60 ps rms as typical final
outputs measured broadband (from 10 Hz to 1 GHz). The
feedback APLL (APLL3) is selected by default; it provides
improved performance over the digital feedback.
Each APLL has its own divider. Each divider
simultaneously outputs a series of fixed ratios of its APLL
input. These divided outputs are available on Output Ports
O1 to O6.
Outputs
The ACS8595 delivers eight output signals on the
following ports: Six clocks, one each on ports O1 to O6;
and two Sync signals, on ports FrSync and MFrSync.
Outputs O1 to O6 are independent of each other and are
Revision 2.00/October 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
DS3/E3 support (44.736 MHz / 34.368 MHz)
independent of rates from DPLL1
Can provide the source for the 2 kHz and 8 kHz
outputs available at Outputs 01 to 06
Can use its phase detector to measure the input
phase difference between two inputs
Selectable digital feedback, on/off
• Low jitter E1/DS1 options independent of rates
• Frequencies of n x E1/DS1 including 16 and 12 x
• Squelched (clock off)
from DPLL1
E1, and 16 and 24 x DS1 supported
FINAL
Page 6
individually selectable. Output 01 is a differential port
(pins O1POS and O1NEG), and can be selected PECL or
LVDS. All other outputs are TTL/CMOS.
Table 5 Output Port Frequencies and Technologies
Table 6 Output Frequencies/Lowest Jitter Configuration
(Typical Conditions)
O1
O2, O3, O4,
O5 and O6
FrSync
MFrSync
2 kHz
8 kHz
1.536
1.544
2.048
2.0586667
2.316
2.7306667
2.796
3.088
3.728
4.096
4.296
4.86
5.728
6.144
6.176
6.48
8.192
8.2346667
9.264
10.922667
11.184
12.288
12.352
16.384
16.46933
17.184
18.528
19.44
21.84533
22.368
24.576
24.704
25.92
32.768
34.368
37.056
Port Name
(not O5/O6)
(not O5/O6)
(not O5/O6)
(not O5/O6)
via Digital1 or Digital2 (not O1)
(not O5/O6)
(not O5/O6)
LVDS/PECL
(LVDS default)
TTL/CMOS
TTL/CMOS
TTL/CMOS
Output Port
Technology
Frequency (MHz)
Frequencies as per Table 6
FrSync, 8 kHz programmable pulse width and
polarity, see Reg. 7C.
MFrSync, 2 kHz programmable pulse width and
polarity, see Reg. 7C.
ACS8595 ATCA
Frequencies Supported
PRODUCT BRIEF
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60
60
250
150
220
150
110
220
110
110
110
3800
120
60
120
250
150
60
220
760
110
250
110
250
110
220
760
120
110
60
250
110
250
110
60
220
120
110
rms (ps)
Jitter Level (typ)
0.6
0.6
1.5
1.0
1.2
1.0
0.75
1.2
1.0
0.75
1.0
13
1.0
0.6
1.0
1.5
1.0
0.6
1.2
2.6
0.75
1.6
1.0
1.5
0.75
1.2
2.6
1.0
0.75
0.6
1.6
1.0
1.5
0.75
0.6
1.2
1.0
0.75
p-p (ns)