ADP3155 Analog Devices, ADP3155 Datasheet - Page 6

• Manufacturer Part Number: ADP3155
• Description: 5-Bit Programmable Triple Power Supply Controller for Pentium III Processors
• Manufacturer: Analog Devices

ADP3155
THEORY OF OPERATION
The ADP3155 uses a current-mode, constant-off-time control
technique to switch a pair of external N-channel MOSFETs in
a synchronous buck topology. Constant off-time operation
offers several performance advantages, including that no slope
compensation is required for stable operation. A unique feature
of the constant-off-time control technique is that since the off-
time is fixed, the converter’s switching frequency is a function
of the ratio of input voltage to output voltage. The fixed off-
time is programmed by the value of an external capacitor con-
nected to the C
regulated output voltage is maintained as described below in the
cycle-by-cycle operation. Under fixed operating conditions the
on-time does not vary, and it varies only slightly as a function of
load. This means that switching frequency is fairly constant in
standard VRM applications. In order to maintain a ripple cur-
rent in the inductor that is independent of the output voltage
(which also helps control losses and simplify the inductor de-
sign), the off-time is made proportional to the value of the out-
put voltage. Normally, the output voltage is constant and,
therefore, the off-time is constant as well.
Active Voltage Positioning
The output voltage is sensed at the SENSE– pin. A voltage-
error amplifier, (g
voltage and a programmable reference voltage. The reference
voltage is programmed to between 1.3 V and 3.5 V by an inter-
nal 5-bit DAC, which reads the code at the voltage identifica-
tion (VID) pins. (Refer to Table I for output voltage vs. VID pin
code information.) A unique supplemental regulation technique
called active voltage positioning with optimal compensation
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a load transient. Stan-
dard (passive) voltage positioning, sometimes recommended for
use with other architectures, has poor dynamic performance
which renders it ineffective under the stringent repetitive tran-
sient conditions specified in Intel VRM documents. Conse-
quently, such techniques do not allow the minimum possible
number of output capacitors to be used. Optimally compen-
sated active voltage positioning as used in the ADP3155 pro-
vides a bandwidth for transient response that is limited only by
parasitic output inductance. This yields optimal load transient
response with the minimum number of output capacitors.
Figure 13. Closed-Loop Test Circuit for Accuracy
1.2V
5-BIT CODE
4700pF
100k
1k
T
pin. The on-time varies in such a way that a
m
OP27
), amplifies the difference between the output
0.1 F
CMP
C
VID0–
VID4
SD
T
AGND
ADP3155
PGND
SENSE+
SENSE–
DRIVE1
DRIVE2
V
CC
12V
1 F
V
OUT
0.1 F
–6–
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator (CMPI)
are the main control elements. (See the block diagram of Figure
3.) During the on-time of the high side MOSFET, CMPI moni-
tors the voltage between the SENSE+ and SENSE– pins. When
the voltage level between the two pins reaches the threshold level
V
turns off the high side MOSFET. The timing capacitor C
then discharged at a rate determined by the off-time controller.
While the timing capacitor is discharging, the low side drive
output goes high, turning on the low side MOSFET. When the
voltage level on the timing capacitor has discharged to the thresh-
old voltage level V
The output of the flip-flop forces the low side drive output to go
low and the high side drive output to go high. As a result, the low
side switch is turned off and the high side switch is turned on.
The sequence is then repeated. As the load current increases, the
output voltage starts to decrease. This causes an increase in the
output of the voltage-error amplifier, which, in turn, leads to an
increase in the current comparator threshold V
the load current. To prevent cross conduction of the external
MOSFETs, feedback is incorporated to sense the state of the driver
output pins. Before the low side drive output can go high, the
high side drive output must be low. Likewise, the high side drive
output is unable to go high while the low side drive output is high.
T1
, the high side drive output is switched to ground, which
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Table I. Output Voltage vs. VID Code
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
T2
, comparator CMPT resets the SR flip-flop.
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
No CPU–Shutdown
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
OUT
T1
, thus tracking
REV. A
T
is