ADP3163 Analog Devices, ADP3163 Datasheet - Page 7

• Manufacturer Part Number: ADP3163
• Description: 5-Bit Programmable 2-/3-Phase Synchronous Buck Controller
• Manufacturer: Analog Devices

Active Current Sharing
The ADP3163 ensures current balance in all the active phases
by sensing the current through a single sense resistor. During
one phase's ON time, the current through the respective high
side MOSFET and inductor is measured through the sense
resistor. When the comparator threshold is reached, the high side
MOSFET turns off. On the next cycle the ADP3163 switches to
the next phase. The current is measured with the same sense
resistor and the same internal comparator, ensuring accurate
matching. This scheme is immune to imbalances in the MOSFET’s
R
If for some reason one of the phases fails, the other phases will
still be limited to their maximum output current (one over the
total number phases times the total short circuit current limit).
If this is not sufficient to supply the load, the output voltage will
droop and cause the PWRGD output to signal that the output
voltage has fallen out of its specified range. If one of the phases
has an open circuit failure, the ADP3163 will detect the open
phase and signal the problem via the PWRGD pin (see Power
Good Monitoring section).
Current Sharing in Multi-VRM Applications
The ADP3163 includes a SHARE pin to allow multiple VRMs
to accurately share load current. In multiple VRM applications,
the SHARE pins should be connected together. This pin is a
low impedance buffered output of the COMP pin voltage. The
output of the buffer is internally connected to set the threshold
of the current sense comparator. The buffer has a 400 A sink
current, and a 2 mA sourcing capability. The strong pull-up
allows one VRM to control the current threshold set point for
all ADP3163s connected together. The ADP3163’s high accuracy
current set threshold ensures good current balance between
VRMs. Also, the low impedance of the buffer minimizes noise
pick up on this trace which is routed to multiple VRMs. This
circuit operates in addition to the active current sharing between
phases of each VRM described above.
Short Circuit Protection
The ADP3163 has multiple levels of short circuit protection to
ensure fail-safe operation. The sense resistor and the maximum
current sense threshold voltage given in the specifications set the
peak current limit.
When the load current exceeds the current limit, the excess current
discharges the output capacitor. When the output voltage is below
the foldback threshold, V
current is cut by reducing the current sense threshold from
the current limit threshold, V
V
tor frequency is reduced by a factor of five when the output is
0 V. This further reduces the average current in short circuit.
Power Good Monitoring
The Power Good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indicates
that the output voltage is within the specified range of the nomi-
nal output voltage requested by the VID DAC. PWRGD will go
low if the output is outside this range.
Short circuits in a VRM power path are relatively easy to detect
in applications where multiple VRMs are connected to a common
power plane. VRM power train open failures are not as easily
spotted, since the other VRMs may be able to supply enough
total current to keep the output voltage within the Power Good
DS(ON)
CS(FOLD)
and inductor parasitic resistance.
. Along with the resulting current foldback, the oscilla-
FB(LOW)
CS(CL)
, the maximum deliverable output
, to the foldback threshold,
voltage specification even when one VRM is not functioning.
The ADP3163 addresses this problem by monitoring both the
output voltage and the switch current to determine the state of
the PWRGD output.
The output voltage portion of the Power Good monitor domi-
nates; as long as the output voltage is outside the specified
window, PWRGD will remain low. If the output voltage is
within specification, a second circuit checks to make sure that
current is being delivered to the output by each phase. If no
current is detected in a phase for three consecutive cycles, it is
assumed that an open circuit exists somewhere in the power
path, and PWRGD will be pulled low.
Output Crowbar
The ADP3163 includes a crowbar comparator that senses when
the output voltage rises higher than the specified trip threshold,
V
both PWM outputs low. The driver ICs turn off the high side
MOSFETs and turn on the low side MOSFETs, thus pulling
the output down as the reversed current builds up in the induc-
tors. If the output overvoltage is due to a short of the high side
MOSFET, this action will current limit the input supply or blow
its fuse, protecting the microprocessor from destruction. The
crowbar comparator releases when the output drops below the
specified reset threshold, and the controller returns to normal
operation if the cause of the over voltage failure does not persist.
Output Disable
The ADP3163 includes an output disable function that turns off
the control loop to bring the output voltage to 0 V. Because an
extra pin is not available, the disable feature is accomplished by
pulling the COMP pin to ground. When the COMP pin drops
below 0.8 V, the oscillator stops and all PWM signals are driven
low. When in this state, the reference voltage is still available.
The COMP pin should be pulled down with an open drain
structure capable of sinking at least 2 mA.
APPLICATION INFORMATION
The design parameters for a typical Intel Pentium 4 CPU appli-
cation are as follows:
CT Selection—Choosing the Clock Frequency
The ADP3163 uses a fixed-frequency control architecture. The
frequency is set by an external timing capacitor, CT. The clock
frequency and the state of the PC pin determine the switching
frequency, which relates directly to switching losses and the
sizes of the inductors and input and output capacitors. With PC
tied to REF, a clock frequency of 600 kHz sets the switching
frequency of each phase, f
practical trade-off between the switching losses and the sizes of
the output filter components. To achieve a 600 kHz oscillator
frequency, the required timing capacitor value is 150 pF. For
good frequency stability and initial accuracy, it is recommended
to use a capacitor with low temperature coefficient and tight
CROWBAR
VID setting voltage (V
Nominal output voltage at no load (V
Nominal output voltage at 65 A load (V
Static output voltage drop based on a 1.5 m load line
(R
Input voltage (V
1.475 V – 1.377 V = 98 mV
Maximum Output Current (I
Number of Phases (n) = 3
OUT
) from no load to full load (V ) = V
. This comparator overrides the control loop and sets
IN
) = 12 V
VID
SW
) = 1.5 V
, to 200 kHz, which represents a
O
) = 65 A
ONL
OFL
) = 1.475 V
ONL
) = 1.377 V
ADP3163
– V
OFL
=