AD9851 Analog Devices, AD9851 Datasheet - Page 12

• Manufacturer Part Number: AD9851
• Description: CMOS 180 MHz DDS/DAC Synthesizer
• Manufacturer: Analog Devices

Figure 20 shows a normal 40-bit serial word load sequence with
W33 always set to Logic 0 and W34 set to Logic 1 or Logic 0 to
control the power-down function. The logic states of the remain-
ing 38 bits are unimportant and are marked with an X, indicating
“don’t care” status. To power down, set W34 = 1. To power up
AD9851
*This bit is always Logic 0.
W0
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
a. DAC Output
Freq–b0 (LSB)
Freq–b1
Freq–b2
Freq–b3
Freq–b4
Freq–b5
Freq–b6
Freq–b7
Freq–b8
Freq–b9
Freq–b10
Freq–b11
Freq–b12
IOUT
V
DD
IOUTB
Figure 19. Serial-Load Frequency/Phase Update Sequence
DATA (7) –
W CLK
Figure 20. Serial-Load Power-Down\Power-Up Sequence
DATA
FQ UD
Table III. 40-Bit Serial-Load Word Functional Assignment
W CLK
FQ UD
b. Comparator Output
Figure 21. I/O Equivalent Circuits
V
DD
W0 = X
W0
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
DIGITAL
OUT
W33 = 0
W1
40 W_CLK RISING EDGES
40 W CLK CYCLES
–12–
Freq–b13
Freq–b14
Freq–b15
Freq–b16
Freq–b17
Freq–b18
Freq–b19
Freq–b20
Freq–b21
Freq–b22
Freq–b23
Freq–b24
Freq–b25
Freq–b26
W34 = 1
W2
OR 0
from a powered down state, change W34 to Logic 0. Wake-up
from power-down mode requires approximately 5 s.
Note: The 40-bit input register of the AD9851 is fully program-
mable while in the power-down mode.
VINP/
c. Comparator Input
VINN
W35 = X
W3
W38 = X
V
DD
W39 = X
W39
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
W38
W39
DIGITAL
d. Digital Input
IN
Freq–b27
Freq–b28
Freq–b29
Freq–b30
Freq–b31 (MSB)
6 REFCLK Multi-
plier Enable
Logic 0*
Power-Down
Phase–b0 (LSB)
Phase–b1
Phase–b2
Phase–b3
Phase–b4 (MSB)
V
DD
REV. C