MAX1068 Maxim Integrated Products, MAX1068 Datasheet - Page 19

• Manufacturer Part Number: MAX1068
• Description: (MAX1067 / MAX1068) 200ksps Analog-to-Digital Converters
• Manufacturer: Maxim Integrated Products

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Figure 13. SPI Internal Clock Mode,16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
Figure 14. SPI Internal Clock Mode, 8-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing
sition. Use the EOC high-to-low transition as the signal
to restart the external clock (SCLK). To read the entire
conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occurring after the conversion result has
been clocked out and prior to the rising edge of CS,
cause the conversion result to be shifted out again. The
MAX1067/MAX1068 internal clock 8-bit-wide data-
transfer mode requires 24 external clock cycles and 25
internal clock cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
conversion immediately aborts the conversion and
places the MAX1067/MAX1068 in shutdown.
INTERNAL
INTERNAL
Multichannel, 14-Bit, 200ksps Analog-to-Digital
STATE
STATE
DOUT
DOUT
SCLK
SCLK
ADC
ADC
EOC
EOC
CLK
CLK
DIN
DIN
CS
CS
X = DON
DSPR = DSEL = DV
MSB
X = DON
DSPR = DV
CSW
1
1
DATA
CONFIGURATION
,
T CARE
• • •
CONFIGURATION
). Forcing CS high in the middle of a
,
T CARE
______________________________________________________________________________________
DD
, DSEL = GND (MAX1068 ONLY)
8
DD
9
X X X X X X X X
• • •
LSB
16
1
8
2
2
t
ACQ
t
ACQ
• • •
6
• • •
13
t
CONV
• • •
24
t
CONV
26
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1067/MAX1068 in the internal clock mode. Enable
scanning by setting bits 4 and 3 in the command/con-
figuration/control register (see Tables 3 and 4). In scan
mode, conversion results are stored in memory until the
completion of the last conversion in the sequence.
Upon completion of the last conversion in the
sequence, EOC transitions from high to low to indicate
the end of the conversion and shuts down the internal
oscillator. Use the EOC high-to-low transition as the sig-
nal to restart the external clock (SCLK). DOUT provides
the conversion results in the same order as the channel
conversion process. The MSB of the first conversion is
available at DOUT on the falling edge of EOC (Figure 14).
t
32
ACQ
MSB
17
30
• • •
t
POWER-DOWN
CONV
48
MSB
9
24
Converters
POWER-DOWN
• • •
• • •
LSB
LSB
S1 S0
S1 S0
40
32
X
X
19