MAX107 Maxim, MAX107 Datasheet - Page 14

• Manufacturer Part Number: MAX107
• Description: Dual / 6-Bit / 400Msps ADC with On-Chip / Wideband Input Amplifier
• Manufacturer: Maxim

designed for single-ended, low-phase noise sine-wave
clock signals with as little as 500mVp-p amplitude
(-2dBm).
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase noise sine-wave source into a single
clock input
mance of the converter is unaffected by clock-drive
power levels from -2dBm (500mVp-p clock signal
amplitude) to +10dBm (2Vp-p clock signal amplitude).
The MAX107 dynamic performance specifications are
determined by a single-ended clock drive of -2dBm
Dual, 6-Bit, 400Msps ADC with On-Chip,
Wideband Input Amplifier
Figure 3. Single-Ended to Differential Conversion Using a Balun
14
Figure 4. Single-Ended Clock Input With AC-Coupled Input
Drive (CLK, INI, INQ)
SIGNAL SOURCE
*TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50Ω TO AGND) ON A
BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS.
______________________________________________________________________________________
FROM SIGNAL SOURCE
50Ω
(Figure 4). Essentially, the dynamic perfor-
A
Single-Ended Clock (Sine-Wave Drive)
180°
0°
50Ω
D
C
50Ω
50Ω
AGND
0°
0°
100pF
100pF
AGND
100pF
100pF
B
AGND
50Ω*
AGND
AGND
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
(500mVp-p clock signal amplitude). To avoid saturation
of the input amplifier stage, limit the clock power level
to a maximum of +10dBm.
The advantages of differential clock drive (Figure 5)
can be obtained by using an appropriate balun or
transformer to convert single-ended sine-wave sources
into differential drives. Refer to Single-Ended Clock
Inputs (Sine-Wave Drive) for proper input amplitude
requirements.
The innovative input architecture of the MAX107 clock
also allows these inputs to be driven by LVDS-, ECL- or
PECL-compatible input levels, ranging from 500mVp-p
to 2Vp-p (Figure 6).
The MAX107 features a 6:12 demultiplexer, which
reduces the output data rate (including DREADY and
DOR signals) to one-half of the sample clock rate. The
demultiplexed outputs are presented in dual 6-bit two’s
complement format with two consecutive samples in
the primary and auxiliary output ports on the rising
Figure 6. LVDS Input Drive (CLK, INI, INQ)
Figure 5. Differential, AC-Coupled Input Drive (CLK, INI, INQ)
TO 50Ω-TERMINATED
SIGNAL SOURCE
OR BALUN
SIGNAL
SOURCE
INPUT
LVDS LINE DRIVER
50Ω TRANSMISSION LINES
50Ω TRANSMISSION LINES
Differential Clock (Sine-Wave Drive)
50Ω
50Ω
LVDS, ECL and PECL Clock
Timing Requirements
AGND
100Ω
100pF
100pF
100pF
100pF
AGND
CLK-,
INI-,
INQ-
CLK+,
INI+,
INQ+
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-