MAX11803 Maxim Integrated Products, MAX11803 Datasheet - Page 41

• Manufacturer Part Number: MAX11803
• Description: (MAX11800 - MAX11803) Ultra-Small Resistive Touch-Screen Controllers
• Manufacturer: Maxim Integrated Products

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The read sequence does not limit the number of bytes to
be read. The internal register counter keeps increment-
ing as additional bytes are requested. The first byte out
is Reg(N) as shown in Figure 24. The next byte out is
Reg(N+1). The next byte out is Reg(N+2), and so on.
The programmer needs to keep track of the incremented
register address. Acknowledge pulses from the master
are not required to autoincrement the internal register
location. The internal register location updates on each
byte. See the Command and Register Map section for
details governing the incrementing of register addresses.
The autoincrement reads only the X, Y, Z1, Z2, and
AUX result registers preventing inadvertent readback of
unrelated or reserved data locations. For example, if
beginning at the XMSB register, a user can cycle
through the XLSB register to the YMSB register and so
forth up to the AUXLSB register. The MAX11801/
MAX11803 do not autoincrement beyond the AUXLSB
register. If clock cycles continue to be given, the
AUXLSB register readback is repeated.
The FIFO (MAX11801) register does not autoincrement,
which allows multiple readbacks of the same location.
This allows the access to multiple FIFO memory blocks
with a single read operation. When reading back FIFO
registers, data management is handled in blocks not
bytes. As a result, when an I
at least one cycle for readback of the first byte of a FIFO
block, the entire block is marked as read. This is regard-
less of whether the block or even byte readback is run
to completion.
Figure 24. I
Figure 25. I
Low-Power, Ultra-Small Resistive Touch-Screen
SDA
SCL
SDA
SCL
START
2
2
1
START
C Streamlined Register Read Sequence
C Multiple Register Read Sequence
I
2
BYTE 1: DEVICE ADDRESS
0
C Configuration or Result Register Read
WRITE ADDRESS
0
1
1
0
______________________________________________________________________________________
A1 A0
BYTE 3: DEVICE ADDRESS
0
WRITE ADDRESS
0
W
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
1
A
N
WRITE REGISTER START NUMBER
BYTE 2: FIRST REG NUMBER = N
0
2
N
C read operation supplies
A1 A0
N
(MAX11801/MAX11803)
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
N
N
Controllers with I
R
N
N
A
N
D
A
BYTE 4: REG(N)[7:0] DATA
D
REPEATED
START
D
READ DATA
1
D
BYTE 3: DEVICE ADDRESS
0
D
WRITE ADDRESS
0
D
1
0 A1 A0
D
D
ACKNOWLEDGE GENERATED BY I
The MAX11801/MAX11803 support several streamlined
readback behavior to significantly improve data transfer
efficiency. Using the streamlined readback sequence
shown in Figure 25, data readback can commence fol-
lowing an assumed progression. Disable the stream-
lined readback feature to allow full readback sequence.
When readback operations are suspended and later
resume from the current (incremented) register loca-
tion, it is not necessary to supply the initial device
address and register start sequence. Begin the read-
back portion of the command following the streamlined
sequence shown in Figure 25 to allow more efficient
data transfer.
For example, if the user accesses the FIFO register
(MAX11801), which does not autoincrement, and reads
several observations and then stops and resumes the
readback operation at a later time, the user only needs
to issue the streamlined readback sequence to contin-
ue to gather observations from the FIFO. Once the
device is placed in autonomous mode, the user only
needs to issue the full readback sequence once for the
initial FIFO access. Then streamlined read access to
the device resumes at the FIFO location, unless an
intervening command is issued as shown in Figure 25.
Similarly, when reading back result registers, begin with
XMSB and autoincrement to XLSB, then stop. When
readback resumes by the issuance of the streamlined
readback sequence, data readback commences from
the YMSB location.
R
A
• Streamlined I
• Resumed
A
ACKNOWLEDGE GENERATED BY I
MAX11803)
MAX11803)
D
SEQUENTIAL READ
D
BYTE 4: REG(N)[7:0] DATA
DATA BYTES
READ DATA
ADDITONAL
D
READ DATA
D
D
2
C MASTER
D
D
2
D
Read
A
2
C/SPI Interface
D
C Read Operations (MAX11801/
2
C MASTER
SEQUENTIAL READ
D
ADDITONAL
DATA BYTES
READ DATA
READ DATA (LAST BYTE)
D
Operations
D
D
D
D
D
READ DATA (LAST BYTE)
D
D
D
D
D
~A
D
(MAX11801/
D
D
~A
STOP
STOP
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