MAX1185 Maxim, MAX1185 Datasheet - Page 13

• Manufacturer Part Number: MAX1185
• Description: Dual 10-Bit / 20Msps / +3V / Low-Power ADC with Internal Reference and Multiplexed Parallel Outputs
• Manufacturer: Maxim

Figure 3. Timing Diagram for Multiplexed Outputs
Figure 4. Output Timing Diagram
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers that follows
Internal Reference and Multiplexed Parallel Outputs
D0A/B–D9A/B
CHB
D0A/B-D9A/B
CLK
CHA
t
OUTPUT
t
DA/B
A/B
DOB
OE
Dual 10-Bit, 20Msps, +3V, Low-Power ADC with
t
CL
CHB
D0B
HIGH-Z
Applications Information
t
CLK
______________________________________________________________________________________
t
ENABLE
t
CH
CHA
D1A
DD
t
/2 output voltage for level
DOA
CHB
D1B
VALID DATA
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
t
DISABLE
CHA
D2A
CHB
D2B
HIGH-Z
CHA
D3A
CHB
D3B
the amplifiers. The user may select the R
values to optimize the filter performance, to suit a par-
ticular application. For the application in Figure 5, a
R
prevent ringing and oscillation. The 22pF C
acts as a small bypassing capacitor.
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1185 for
optimum performance. Connecting the center tap of the
transformer to COM provides a V
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1185 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
ISO
of 50Ω is placed before the capacitive load to
CHA
D4A
CHB
D4B
Using Transformer Coupling
CHA
D5A
CHB
D5B
DD
/2 DC level shift to
CHA
D6A
ISO
IN
CHB
D6B
capacitor
and C
13
IN