T8503 ETC-unknow, T8503 Datasheet
T8503
Manufacturer Part Number
T8503
Description
T8502 T8503 Dual Codecs With Filters
Manufacturer
ETC-unknow
Datasheet
1.T8503.pdf
(16 pages)
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Data Sheet
July 1998
Features
+5 V only
Two independent channels
Pin-selectable receive gain control
Pin-selectable -law or A-law companding
Automatic powerdown mode
Low-power, latch-up-free CMOS technology
— 40 mW/channel typical operating power
— 12.5 mW/channel typical standby power
Automatic master clock frequency selection
— 2.048 MHz or 4.096 MHz
Independent transmit and receive frame strobes
2.048 MHz or 4.096 MHz data rate
On-chip sample and hold, autozero, and precision
voltage reference
Differential architecture for high noise immunity
and power supply rejection
dissipation
dissipation
VF
VF
VF
VF
GS
GS
X
X
R
R
IN0
IN1
O0
O1
X
X
0
1
T8502 and T8503 Dual PCM Codecs with Filters
–
+
+2.4 V
NETWORK
NETWORK
CHANNEL 0
CHANNEL 1
FILTER
FILTER
Figure 1. Block Diagram
ENCODER
DECODER
Description
The T8502 and T8503 devices are single-chip, two-
channel, -law/A-law PCM codecs with filters. These
integrated circuits provide analog-to-digital and
digital-to-analog conversion. They provide the
transmit and receive filtering necessary to interface a
voice telephone circuit to a time-division multiplexed
system. These devices are packaged in both 20-pin
SOJs and 20-pin SOGs.
The T8502 differs from the T8503 in its timing mode.
The T8502 operates in the delayed timing mode
(digital data is valid one clock cycle after frame sync
goes high), and the T8503 operates in the
nondelayed timing mode (digital data valid when
frame sync goes high) (see Figures 5 and 6).
Meets or exceeds ITU-T G.711—G.714 require-
ments and VF characteristics of D3/D4 (as per
Bellcore PUB43801)
Operating temperature range: –40 C to +85 C
INTERNAL TIMING
REFERENCE
INTERFACE
CIRCUITRY
& CONTROL
CONTROL
PCM
GAIN
BIAS
&
D
D
FS
FS
FS
FS
GNDD
GS0
GS1
MCLK
ASEL
V
GNDA (2)
X
R
DD
X
R
X
R
0
1
0
1
5-3579.b
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