ATA6622 ATMEL Corporation, ATA6622 Datasheet - Page 15

• Manufacturer Part Number: ATA6622
• Description: LIN Bus Transceiver with 3.3V (5V) Regulator and Watchdog
• Manufacturer: ATMEL Corporation

6. Watchdog
6.1
4986B–AUTO–07/07
DRAFT
Typical Timing Sequence with R
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge)
input within a time window of T
t
NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period,
T
During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES
disappears. It is defined as lead time t
t
The trigger signal T
R
For example, with an external resistor of R
watchdog are as follows:
t
t
t
t
t
t
After ramping up the battery voltage, the 5V regulator is switched on. The reset output NRES
stays low for the time t
the trigger sequence from the microcontroller. The lead time, t
t
ger pulse NTRIG occurs during this time, the time t
occurs during the time t
t
from the microcontroller is anticipated within the time frame of t
gering from glitches, the trigger pulse must be longer than t
restart the watchdog sequence. If the triggering signal fails in this open window t
output will be drawn to ground. A triggering signal during the closed window t
switches NRES to low.
d
osc
OSC
d
1
2
nres
d
d
trigmin
osc
WD_OSC
starts with the negative edge of the RXD output.
= 7895 × 19.6 µs = 155 ms
= 1053 × 19.6 µs = 20.6 ms
= 1105 × 19.6 µs = 21.6 ms
= 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trig-
= 155 ms. The times t
= 0.405 × R
, is adjustable via the external resistor R
= constant = 4 ms
= 19.6 µs due to 51 kΩ
> 200 ns. If a triggering signal is not received, a reset signal will be generated at output
.
ATA6622/ATA6624/ATA6626 [Preliminary]
WD_OSC
wd
WD_OSC
reset
– 0.0004 × (R
d
1
is adjustable between 20 ms and 64 ms using the external resistor
, a watchdog reset with t
and t
(typically 4 ms), then it switches to high, and the watchdog waits for
2
have a fixed relationship between each other. A triggering signal
= 51 kΩ
w d
WD_OSC
d
. The trigger signal must exceed a minimum time
. After wake up from Sleep or Silent Mode, the lead time
)
WD_OSC
wd_osc
2
(R
WD_OSC
NRES
(34 kΩ to 120 kΩ).
= 51 kΩ ±1%, the typical parameters of the
1
= 4 ms will reset the microcontroller after
in kΩ; t
starts immediately. If no trigger signal
TRIG,min
osc
2
= 21.6 ms. To avoid false trig-
> 200 ns. This slope serves to
in µs)
d
, follows the reset and is
1
2
immediately
, the NRES
15